Glass in semiconductors technology benchmarks & analysis, supply-chain deep dive, market forecasts across carrier, panel, IC-substrate, interposer, IPD, RF-MEMS & photonic glass segments, challenges, opportunities and adoption outlook

 

Glass in semiconductors is not a moon-shot concept; it already sits quietly inside modern fab. Ultra-flat borosilicate carriers hold silicon wafers during backside thinning, sodium-free sheets form hermetic MEMS caps, and low-coefficient of thermal expansion (CTE) glass is the baseplate for many wafer-level fan-out processes.

 

Glass is gradually moving from a background consumable to the heart of a package, providing the core substrate, the interposer that links chiplets, and the dielectric that shapes sub-THz signals or steers photons on their way to optical fiber.

 

The catalyst is the escalating bandwidth and power density of AI and high-performance-computing devices. A single training accelerator already requires thousands of high-speed I/O bumps and a power-delivery network that handles hundreds of amps with minimal noise. Organic-based laminate, the workhorse of the last twenty years, struggles to keep the required flatness and via density with ever increasing demand. Silicon interposers offer far finer wiring, but at a price and panel size that limited applications can justify.

 

Glass slides neatly between these extremes. Its coefficient of thermal expansion can be tailored to match silicon; its loss tangent is an order of magnitude lower than silicon at 40 GHz, and large-panel processing potential from the LCD industry means a single sheet can be half a meter on one side at costs that trend towards high-end organics as yields rise. The surging demand for AI and high-performance computing is forcing every layer of the packaging stack to carry more current, more I/O, and higher signaling speeds than organic laminates or even first-generation silicon interposers can comfortably support. These pressures have turned glass core substrates and large-panel glass interposers from a niche curiosity into commercialization. Leading device makers and materials vendors are now openly investigating the technology: Intel has demonstrated glass-based test vehicles on its Arizona path-finding line, Samsung Electronics is exploring glass cores as a potential option alongside its I-Cube and H-Cube packages, substrate major SKC has installed a pilot drill-and-fill line for 500 mm glass panels, and glass giant AGC is supplying low-CTE borosilicate sheets for early evaluations. No company has yet nailed down a production launch date, but the collective effort signals a clear shift—glass is firmly on the shortlist of next-generation substrate candidates for the AI/HPC era. The trend is reflected by the emergence of glass core substrate and interposers, especially for advanced packaging and IC substrates.

 

Glass's low dielectric loss and optical transparency give it a second growth engine beyond compute packaging. At Ka-band and above, insertion loss through a glass microstrip is roughly half that of an equivalent organic line.

 

Photonics adds still another pull. Co-packaged optics (CPO) aims to move fiber attach from the front panel of a switch to the substrate that sits millimeters from the switch ASIC. Engineered glass can carry both the electrical redistribution layers and the low-loss waveguides, simplifying alignment and eliminating costly silicon photonic interposers. Because the same through-glass via (TGV) technology used for RF can create vertical optical vias, a single core can support trans-impedance amplifiers, laser drivers, and the optical waveguide itself. This convergence of electronic and photonic routing plays directly to glass's strengths and pushes its potential market beyond conventional electronics packaging.

 

 

 

Why supply-chain insight matters now

What this report delivers

Who should read

Key Aspects

• End-to-end market intelligence for seven distinct glass product segments, with unit and revenue forecasts 2025-2036.
• Technology deep dives: TGV drilling, metallization, panel-level processing, manufacturing, etc.
• Benchmarking of glass vs. organic and silicon interposers/substrate for speed, loss, warpage & cost.
• Supply-chain mapping from glass melt facilities to OSAT panel lines, highlighting announced capacities.
• Adoption drivers in AI/HPC, 5G/6G RF front-ends, HBM memory, photonic interposers, MEMS & sensor caps.
• Risk analysis: yield learning, challenges, and competing substrate roadmaps.
• Detailed discussion of glass in photonics (co-packaged optics, micro-lens arrays) and high-frequency applications.

 

1.1. Glass materials

1.2. Applications of glass in semiconductors

1.3. Glass for advanced packaging

1.4. Glass used in various semiconductor applications

1.5. Opportunities ahead with glass packaging

1.6. Key advantages of glass substrates

1.7. Challenges in adopting glass substrates

1.8. Future market trends

1.9. Future development directions: Advanced processing technologies

1.10. Future development directions: Integrated packaging solutions & Sustainable manufacturing initiatives

1.11. Beneficiaries of glass core substrate introduction

1.12. Value chain of glass substrate

1.13. Value chain shift from organic to glass core substrate

1.14. Future outlook

1.15. Material innovations

1.16. Investment priority areas

1.17. Activities of representative players

 

2.1. Market forecast segmentation

2.2. Market forecast methodology

2.3. Unit shipment forecast 2025-2036

2.4. Market value forecast 2025-2036

2.5. Market trends

2.6. 2025 vs. 2036 markets

2.7. Market and economic factors

 

3.1. Dimensionality of advanced packaging

3.2. From 1D semiconductor packaging

3.3. Advanced packaging 2D & 2D+

3.4. Advanced packaging 2.5D & 3D

3.5. Advanced packaging 3.5D & 4D

3.6. Technology development trend for 2.5D and 3D packaging

3.7. Intel's advanced packaging roadmap

3.8. Heterogeneous integration solutions

3.9. Overview of System on Chip (SOC)

3.10. Overview of Multi-Chip Module (MCM)

3.11. System in Package (SiP)

3.12. Analysis of System in Package (SiP)

3.13. Glass IC substrates

3.14. From Organic to Glass Core Substrate

3.15. Evolution of packaging substrates in semiconductors

3.16. From organic to glass core

3.17. Organic core substrate vs. glass core substrate

3.18. TSV vs. TGV

3.19. Material property comparison for advanced packaging

3.20. Key mechanical and reliability benefits of glass

3.21. I/O density

3.22. Key factors enabling fine circuit patterns on glass substrates

3.23. Fine circuit patterning reduces DoF

3.24. FC-BGA substrates lead to larger distortions

3.25. Limitations of Via formation

3.26. SAP method limitations

3.27. PCB stack-ups

3.28. Traditional multilayer vs. build-up PCBs

3.29. Build-up material: ABF

3.30. ABF substrate manufacturing process

3.31. Flip Chip Ball Grid Array (FC-BGA) substrate

3.32. Glass core substrate

3.33. Glass core substrate technologies

3.34. Glass interposer vs. silicon interposer

3.35. Through Glass Via Formation

3.36. Through glass via formation process

3.37. Comparison of through glass via formation processes

3.38. TGV process and via formation methods

3.39. Mechanical and high-power laser drilling

3.40. Laser-induced deep etching

3.41. LMCE from BSP

3.42. Philoptics' TGV technology

3.43. Laser-induced modification and advanced wet etching

3.44. Comparison among the TGV processes

3.45. Photosensitive glass and wet etching

3.46. Samtec's TGV technology

3.47. TGV of high aspect ratio

3.48. TGV Metallization

3.49. TGV metallization processes

3.50. Two-step process

3.51. Seed layer deposition in TGV metallization

3.52. Factors for alternative TGV metallization process

3.53. Comparison of TGV metallization processes

3.54. Glass Substrate Manufacturing

3.55. Technology: Organic core substrate vs. glass core substrate

3.56. Glass core substrate: Core layer fabrication

3.57. Glass core substrate: Build-up layer fabrication

3.58. Manufacturing process of glass substrate (CHIMES)

3.59. Achieving 2/2 μm L/S on glass substrate

3.60. Glass fabrication process by Georgia Institute of Technology

3.61. Glass core 3D integration: Georgia Tech's embedded die packaging

3.62. Glass cavity lamination process flow by Georgia Institute of Technology

3.63. Chip-first non-TSV 3D glass panel embedding

3.64. Georgia Institute of Technology test vehicle comparison

3.65. Intel's glass line

3.66. Features of Glass-based Advanced Packaging and IC Substrates

3.67. TGV - Player and products benchmark

3.68. Advanced thermal management for glass packages

3.69. Shifting dynamics and emerging leaders in glass core substrate and interposer patent activity

3.70. Glass substrate adoption innovations in semiconductor packaging

3.71. Glass innovation efforts

3.72. Plan Optik AG

3.73. Plan Optik AG's Technology

3.74. KCC

3.75. Intel's glass substrate efforts

3.76. Absolics' progresses

3.77. CHIMES' focus on glass in advanced packaging

 

4.1. What is a photonic integrated circuit?

4.2. Why PICs?

4.3. Optical coupling - I/O

4.4. EIC/PIC integration

4.5. Co-Packaged Optics

4.6. Co-packaged optics architecture

4.7. Key trend of optical transceiver

4.8. Glass-based CPO integration

4.9. Glass interposer-based CPO architecture

4.10. Ion exchange waveguide formation technology

4.11. Dual-mode glass waveguide performance characteristics

4.12. Adiabatic glass-to-silicon waveguide coupling for CPO integration

4.13. Glass-based fiber connector assembly for CPO applications

4.14. Glass interposer optical signal path architecture

4.15. Glass interposer manufacturing process and laser separation technology

4.16. Corning's high-density 102.4 Tb/s glass integration platform

4.17. 3D integration of EIC/PIC with a glass interposer

4.18. 3D integration of EIC, PIC, ASIC on a co-packaged glass substrate

4.19. Fabrication process of the 3D integration of ASIC, EIC, PIC on a co-packaged substrate

4.20. Advancements in glass integration for photonics

 

5.1. Applications of low-loss materials in semiconductor and electronics packaging

5.2. Transmission loss in high-frequency PCB design

5.3. Glass as a low-loss material

5.4. Categories of RF applications enabled by glass in semiconductor technology

5.5. Benchmark of LTCC and glass materials

5.6. Dielectric constant: Stability vs frequency for different inorganic substrates (LTCC, glass)

5.7. Benchmarking of commercial low-loss materials for 5G PCBs/components

5.8. Five important metrics impacting low-loss materials selection

5.9. Glass suppliers: JSK's HF-F for low transmission loss laminates

5.10. Glass suppliers: SCHOTT's FLEXINITY connect

5.11. Glass suppliers: AGC/ALCAN System's transparent antennas for windows

5.12. Glass as a filter substrate

5.13. Glass integrated passive devices (IPD) filter for 5G by Advanced Semiconductor Engineering

5.14. Glass substrate AiP for 5G: Georgia Tech

5.15. Glass for 6G: Georgia Tech

5.16. Glass interposers for 6G

5.17. Access More With an IDTechEx Subscription