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誘電体前駆体

Dielectric Precursors

TECHCET's Critical Materials Report

 

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Techcet
テクセット社
2020年6月US$8,468
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この調査レポートは、誘電体前駆体市場を詳細に調査し、サプライチェーンや技術動向などを解説しています。

  • Provides market and technical trend information on organic and inorganic precursors, addressing CVD, ALD, and SOD applications including ILDs & low-κ dielectrics, hard masks, sidewall spacers and etch stop layers
  • Provides focused information for supply-chain managers, process integration and R&D directors, as well as business development and financial analysts
  • Covers information about key suppliers, issues/trends in the material supply chain, estimates on supplier market share, and forecast for the material segments


目次

Table of Contents

1 Executive Summary ............ 11

1.1 Precursors Market Forecasts & 5-Year CAGRs .......... 11
1.2 Competitive Landscape ............ 12
1.3 M&A Activities ................. 14
1.4 Precursors & Technology Trends .......... 15
1.5 Supply-Chain Issues .............. 17
1.6 EHS Issues/Concerns ............ 17
1.7 Analyst Assessment ............. 17

2 Scope, Purpose, and Methodology ............. 20

2.1 Scope ................... 20
2.2 Purpose ............... 20
2.3 Methodology ............... 20
2.4 Overview of Other TECHCET CMR Reports ......... 21

3 Semiconductor market outlook .......... 22

3.1 Worldwide Economy ............ 24
Semiconductor Industries Ties to the Global Economy ........ 26
3.2 Electronic Goods Market .............. 28
Smartphones ................ 29
Automotive ............... 30
Servers / IT ................ 34
PCs / Tablets ................. 36
3.3 Semiconductor Industry Outlook .......... 37
Equipment Spending and Fab and Capital Investments ....... 39
Overall China Market News and Trends ........... 41
Wafer Start Forecast ............. 43
3.3.3.1 MEMS & Legacy Devices .............. 43
3.3.3.2 Advanced and Leading Edge Devices .............. 44
3.3.3.3 TECHCET Wafer Start Model Background ........... 46
3.4 Semiconductor Market Overview Summary ......... 47

4 Semiconductor precursors market trends ........... 49

4.1 Advanced Dielectric and Spin on Dielectric precursors ......... 52
4.2 Technical Drivers / Material Changes and Transitions .......... 53
4.3 Leading Edge Logic ............... 54
4.4 DRAM .................. 54
4.5 3DNAND .............. 56
4.6 Emerging Memory Devices ............... 57
4.7 Chip Fab Announcements & Activities .......... 57
Comment on Regional Trends/Drivers ............. 59
Changes in standard packaging/valve types ......... 61

5 Precursors Market Landscape ............ 62

5.1 Fab Material Supply/Demand .............. 62
5.2 Market Share & Regional Ranking ............ 64
5.3 Regional Ranking ................. 65
5.4 M&A Activity ............... 68
Linde-Praxair ................. 68
DowDuPont ............... 69
Versum Materials takeover deal by Merck KGaA ......... 70
The logic behind the Linde-Praxair merger and Merck take over Versum? ..... 70
MPD Chemicals acquires Norquay Technology and then gets acquired by Entegris .... 72
M&A activity in the CVD and ALD OEM segment ......... 73
5.4.6.1 Applied Materials Kokusai take over ............... 73
5.4.6.2 PlasmaTherm acquires KOBUS ............ 75
5.4.6.3 ACM Research Enters Dry Processing Market and Launch of CVD/ALD Ultra Furnace ... 75
Summary of additional merger and take over activities ....... 76
5.5 New Plants and New Entrants .............. 77
Air Liquide to invest ?200 million in Taiwan to support semiconductor manufacturers ..... 77
5.6 Plant Closures and Product Discontinuations ........... 77
5.7 New Entrants ............... 78
MERCK .................. 78
Mitsubishi Chemical Acquiring Gelest .......... 78
5.8 Suppliers or Parts/Product Line That is at Risk of Discontinuations ...... 79
5.9 Precursor IP Filing ................ 80
5.9.1 Dielectric precursor IP .............. 80
5.9.2 ALD IP filing and global distribution of IP ............. 83
5.9.3 Dielectrics and High-κ IP trends ........... 85

6 Supplier profiles ............. 87

Adeka
Kojundo
Tanaka
Air Liquide
Linde
TCI
Azmax Co.
Mercaro
Trichemical Labs
DNF
Merck EMD / Versum
umicore
Entegris
Nanmat
UPChem / Yoke
EpiValence
Norquay / Entegris
Versum / Merck EMD
Gelest
Praxair/ Linde
Wonik
Hansol
SoulBrain
Zillion
HC Starck
Strem

7 APPENDIX A: LOGIC AND MEMORY TECHNOLOGIES BACKGROUND / TREND BASICS FROM TECHCET’s 2019 CMR REPORT ........... 220

7.1 Multi-patterning & EUV Lithography .......... 220
7.2 Interconnect Trends ............... 225
7.3 Copper Interconnect .............. 227
7.3.1 Cobalt interconnects, liners, and caps ............ 228
7.3.2 Ruthenium Interconnects ............... 233
7.3.3 High-aspect-ratio ruthenium power rails ........... 234
7.3.4 Manganese Barrier Metal ............... 235
7.4 Logic Transistor Evolution .............. 235
7.4.1.1 5 nm and beyond ............... 240
7.4.2 Extending FinFET to Horizontal Nanowires GAA FETs ........ 242
7.4.3 Realizing vertical Logic - Going vertical (2.5/3D) ........ 246
7.5 Memory Evolution & Future Trends ........... 249
7.5.1 DRAM .................. 250
7.5.2 2D to 3DNAND transition ............ 255
7.5.3 Alternative NVM Technologies ........... 257

8 APPENDIX B: ACRONYMS ............. 258

TABLE OF FIGURES

Figure 2: The total advanced dielectric and spin-on dielectric precursor market (2014 to 2024) . 12
Figure 3: Global Economy and the Electronics Supply Chain (2019) ........ 27
Figure 4: Worldwide Semiconductor Sales ............ 28
Figure 5: Semiconductor Chip Applications ............. 29
Figure 6: Mobile Phone Shipments WW Estimates ............ 30
Figure 7: Oil Price per Barrel US WTI ............ 32
Figure 8: Semiconductor Spend per Vehicle Type ........... 33
Figure 9: Semiconductor Content by Automotive Application .......... 34
Figure 10: Semiconductor Revenue Growth Forecasts (as of April 19, 2020) .... 38
Figure 11: Semiconductor Units History and Forecast .......... 39
Figure 12: 200 mm Fab Capacity Outlook to 2022 ........... 44
Figure 13: TECHCET Wafer Starts by Technology Node and Device Type ......... 46
Figure 14: PVD, CVD, and ALD chamber shipments 2014 to 2024. ........ 49
Figure 15: IP filing and grants in the CVD and ALD space by OEMs as of November 2019. Please
note that a large part of 2018 and 2019 applications were still in the pipeline due to 18-month
delay. ..................... 50
Figure 16: TECHCET Wafer Starts by Technology Node and Device Type ......... 52
Figure 18: The total advanced dielectric and spin-on dielectric precursor market 2014 to 2024. . 53
Figure 19: Process and materials changes required to shrinking logic down to sub 2 nm. ..... 54
Figure 20: Process and materials changes required to shrinking DRAM down to 10 nm. .... 55
Figure 21: Process and materials changes required to shrinking 3DNAND up to 2xx layers. ... 56
Figure 22: TSMC Fab 18 is the 5nm production facility ......... 58
Figure 24: Xtacking diagram with peripheral controller logic die placed above separate NAND
die .................. 60
Figure 25: ChangXin Memory thus far completed the R&D and Fab 1. ........ 61
Figure 28: TECHCET SOD Precursor Revenue 2014 to 2024 .......... 63
Figure 30 Market Share Of Precursor Companies for Dielectric Precursors(% of total revenues) ... 65
Figure 31 Regional market share of precursor companies for metal and high-k precursors 2019. 66
Figure 32 Regional Market Share Of Precursor Companies for Dielectric Precursors ...... 67
Figure 33: Annual revenue of major gas and chemical companies supplying precursors and
gases to the semiconductor industry. ............... 71
Figure 35: Overview of IP filed in the segment Spatial ALD. ........ 74
Figure 36: Assessment Of The CVD & ALD 8 And 6 Inch Market By OEM ....... 80
Figure 37: The relative age distribution of segmented dielectric precursors filed by OEMs,
chemical companies, fabricators, and research organization in the last two decades. .. 82
Figure 38: Distribution of dielectric precursor IP by OEMs, IDM/Foundries, and Chemical Suppliers.
................... 83
Figure 39: Filed IP in the field of Atomic Layer deposition. .......... 84
Figure 40: Global Filed IP in the field of Atomic Layer deposition. ......... 84
Figure 41: PEALD publications for dielectrics. ........... 85
Figure 42: Dielectric and High-κ IP Applications segmented by a deposition method. .. 86
Figure 62: Double patterning by increases density so-called LELE for “Litho-Etch-Litho-Etch. .. 221
Figure 63: Self-aligned quadruple patterning (SAQP). .......... 221
Figure 64: Hardmask to Prevent Pattern Collapse .......... 222
Figure 65: Dimensional scaling under pressure ........... 223
Figure 66: EPE is the difference between the intended and the printed features of an IC layout.
Shrinking dimensions exacerbate EPE issues. .......... 224
Figure 67: Local and global interconnects. ............ 226
Figure 68: The innovative copper metallization technique by IBM from 1997 produced a chip with
six layers of copper circuitry with circuit line widths of 0.20 microns. ....... 227
Figure 69: Extending copper requires co-optimization of ALD barriers with thinner liners and new
fill technology to maximize conductor volume (low line R) and minimize interface resistance (low
via R). ................... 228
Figure 70: Introduction of Co CVD encapsulation and transition to Cobalt contacts and local
interconnects. ................ 229
Figure 71: Intel Interconnect stack as describes at IEDM 2017(left) and SEM cross-section (right)
and features 12-metal interconnect layers with the bottom two made of cobalt. This is the firsttime
cobalt used in a high-volume production node. .......... 230
Figure 72: 10nm via structure filled with cobalt shows no seams. ......... 231
Figure 73: Apple A11 resp. A12 fabricated using TSMC 10 res. 7 nm showing the introduction of
Co contacts (blue) with the TiN barrier at 7 nm (Apple A12). .......... 232
Figure 74: Applied Materials PVD/ALD/CVD-deposition solution for Cobalt fill. ..... 232
Figure 75: Schematic representation of a buried power rail construct ....... 234
Figure 76: Interconnect Scheme Using ALD Magnesium ilicide ....... 235
Figure 77: The evolution of High-κ / Metal Gate Transistors, from the first planar 45 nm to the 14
nm node. ................. 236
Figure 78: Comparison of CMOS Transistors used today. (A) Planar, (B) FD-SOI, and (C) FinFET. . 237
Figure 79: Possible uses for dielectrics in state of the art 10 nm FinFET Technology: Low-κ, High-κ,
liners, and even dielectric air gaps. ............. 238
Figure 80: Intel 10nm and Foundry 7nm Logic Process nodes compared. ..... 239
Figure 81: After the introduction at 22 nm by Intel, taller fin height and narrower fin width leads to
a more vertical profile in 14 nm and 10 nm. ........... 240
Figure 82: Schematic of partial air spacers (left), and TEM cross-section of FinFET gates, showing
spacers between gates and contacts. .............. 241
Figure 83: A GAA (gate-all-around) FET that could come into play at 5 or 3 nm. ..... 242
Figure 84: Imec CMOS Roadmap to N1 and beyond. .......... 243
Figure 85: Imec has achieved the CMOS integration of vertically stacked gate-all-around (GAA)
silicon nanowire MOSFETs. ................. 244
Figure 86: Three principal Cross-section simulation of (a) finFET, (b) nanowire, and (c) nanosheet.
..................... 245
Figure 87: TEM cross-section of 5nm-node GAA-FETs by IBM, Samsung, and GlobalFoundries. ... 245
Figure 88: Leti roadmap for introducing monolithic 3D Logic scaling at 5 nm ....... 247
Figure 89. Stacking FinFETs on FinFETs. .............. 248
Figure 90: Roadmap for 3D SoC and 3D Logic post 3nm CMOS node. ...... 249
Figure 91: Device integration for current and emerging memory technologies. ...... 250
Figure 92: DRAM capacitor development, historical. ........ 251
Figure 93: COVID-19 impact of the slowdown on different market segments. ...... 252
Figure 94: Cut through a graphics card that uses High Bandwidth Memory ...... 254
Figure 95: Deep Trench Capacitors (DTCs) as eDRAM technology node and cell size trends from
IBM up to date. ................... 255
Figure 96: The implications of the Transition to 3DNAND ........... 256

TABLES

Table 1: TECHCET’s Critical Materials Reports? ........... 21
Table 2: Lockdown & Restrictions by Country (April 2020) .......... 23
Table 3: Global GDP and Semiconductor Revenues .......... 24
Table 4: IMF World Economic Outlook ............... 25
Table 5: 2020 Auto Industry Growth Impact Factors ............ 32
Table 6: Data Center Systems and Communication Services Forecast 2020 ....... 35
Table 7: Worldwide Device Shipments by Device Type, 2020-2022 (Jan 2020) ....... 37
Table 8: 2019 Investment Plans for Selected Device Companies (as of March 2020) ..... 40
Table 9: 2020/ 2019 Growth Estimates for 3DNAN, DRAM and Logic Devices (advanced nodes
and leading edge) .................. 45
Table 10: CVD and ALD OEM Technology as Product. ........... 51
Table 12: Assessment of China's needs for advanced ALD/CVD Precursors .... 60
Table 13. 5-Year CAGR 2019 as compared to 2024 for advanced dielectric precursors. .. 64
Table 14: The Linde-Praxair Merger Divestment of Substantial Business Assets ..... 68
Table 16: Throughput Immersion vs. EUV Lithography. ........... 224
Table 17:: OEM Tool Sets for Sub-5 nm Logic devices ........ 246
Table 18: Critical thermal budget steps summary in a planar FDSOI integration and 3D CoolCube
process for top FET in 3DVLSI. ................ 248

 

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