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誘電体前駆体

Dielectric Precursors

TECHCET's Critical Materials Report

 

出版社 出版年月電子版価格 ページ数
Techcet
テクセット社
2019年6月US$8,468
サイトライセンス
106

サマリー

この調査レポートは、誘電体前駆体市場を詳細に調査し、サプライチェーンや技術動向などを解説しています。

主な掲載内容(目次より抜粋)

  1. エグゼクティブサマリー
  2. 調査範囲
  3. 市場展望
  4. 材料動向
  5. サプライヤの市場環境
  6. サプライヤ情報

The Dielectric Precursors Report provide detailed market, supply chain and technology trend information required for anyone developing strategy for their business, be it a materials supplier or semiconductor chip manufacturer. Precursor types include, gapfill, ILD, low K, and multi-patterning.



目次

Table of Contents

1 Executive Summary ................. 8

1.1 Highlight Material Segment Business Trends (M&A, plant closures, new suppliers, etc.) ... 8
1.2 Highlight Material Segment Technology Trends ............ 10
1.3 5-Year Material Segment Forecast .............. 11
1.4 EHS/Logistics ................... 13
1.5 Concludes with analyst assessment of the covered materials market ....... 14

2 Scope ..................... 15

2.1 Scope...................... 15
2.2 Purpose ..................... 15
2.3 Methodology .................... 15

3 Market Outlook................ 16

3.1 Worldwide Economy .................. 16
3.2 Electronic Goods Market ................ 22
3.3 IT / Data Systems ................. 22
3.4 Smart Phone Market .................. 23
3.5 PC Computers ................... 25
3.6 Automotive ................... 25
3.7 Semiconductor Device Outlook ............... 27
3.8 Equipment Spending and Fab and Capital Investments ........ 30
3.9 MEMS & Legacy Devices ................ 34
3.10 Wafer Start Forecast .................. 35
3.11 Overall China Market News and Trends ............. 37
3.12 Semiconductor Market Overview Summary ............ 39

4 Material Segment Trends.............. 40

4.1 Technical drivers/material change & transitions .......... 40
4.1.1 Material trends for the leading-edge ............. 41
4.1.2 Multi-patterning & EUV Lithography............. 41
4.2 Interconnect Trends ................ 47
4.3 Logic Transistor Evolution ................ 48
4.3.1 5 nm and beyond.................. 54
4.4 Extending FinFET to Horizonal Nanowires GAA FETs ........ 56
4.5 Realizing vertical Logic - Going vertical (2.5/3D) .......... 61
4.6 Memory Evolution & Future Trends ............ 64
4.6.1 DRAM......................64
4.6.2 2D to 3D NAND transition ................ 67
4.6.3 Trends/impact/status of legacy materials ........... 72
4.7 Comment on Regional trends/drivers ............. 74
4.8 EHS and, if possible, Logistics issues* ............ 75
4.9 Changes in standard packaging/valve types ............. 75

5 Supplier Market Landscape .............. 77

5.1 M&A Activity .................... 77
5.1.1 Linde-Praxair .................... 77
5.1.2 DowDuPont ................... 77
5.1.3 Versum Materials takeover deal by Merck KGaA........... 78
5.1.4 MPD Chemicals acquires Norquay Technology .......... 78
5.2 New plants/New entrants ................. 79
5.3 Identify recently closed plants or ”to be” closed plants ......... 79
5.4 New entrants .................... 79
5.4.1 Adekas´new liquid Yttrium precursor ............ 80
5.4.2 Strem Chemicals’ offers new La-FMD ALD precursor for future leading-edge logic and memory products ...................... 81
5.4.3 RASIRC : Effective Silicon and Metal Nitride Deposition at Reduced Temperature using Brute Hydrazine ..................... 82
5.5 Si-Precursors .................... 83
5.5.1 Precursor IP filing .................... 84
5.5.2 Dielectric precursor IP ................ 85
5.5.3 ALD IP filing and global distribution of IP ............ 87
5.5.4 Dielectrics and High-κ IP trends ................89
5.5.5 Cobalt CVD/ALD deposition IP trends .............. 91
5.6 Suppliers or parts/product lines that are at risk of discontinuance or capacity reduction . 93
5.7 Materials Market Size & Forecast ................ 94
5.7.1 Advanced dielectric ALD/CVD/SOD precursors.......... 95
5.7.2 Market Shares and Regional Shares ..............98
5.7.3 TECHCET Analyst Assessment and outlook for raw materials supply-chain issues. 99

6 Supplier Profiles ................ 100

Appendix 1: Copper Interconnect History & Status ..........101
Appendix 2: Fundamentals of thin film deposition by CVD, ALD, and SOD, and ASD and ALE ...103
6.1 Chemical Vapor Deposition - CVD ............. 103
6.2 Atomic Layer Deposition ? ALD ................ 105
6.3 Spin-on Dielectrics (SOD) ................ 105
Appendix 3: Acronyms .................107

List of Figures

Figure 1 TECHCET Wafer Starts by Technology Node and Device Type ? 2/2019 modified to show the high growth nodes concerning ALD, CVD, and SOD. .... 9
Figure 2 : Metal and High-κ Precursor Market Shares by Precursor Type Estimates .. 12
Figure 3 Dielectric Precursor Market Shares by Precursor Type Estimates for 2019 & 2024. ... 13
Figure 4 2018 Global Economy and the Electronics Supply Chain ...... 17
Figure 5 Worldwide Semiconductor Sales ............ 18
Figure 6 Global Purchasing Managers Index ........... 19
Figure 7 Global Electronics Production Annual Growth ......... 22
Figure 8 Global Electronics Production Annual Growth ......... 23
Figure 9 Automotive Electronic Content Growth ............ 26
Figure 10 Automotive Semiconductor Market Growth .......... 27
Figure 11 2019 Semiconductor Revenue Growth Forecasts ........ 28
Figure 12 2019 Semiconductor Market Size by Device Segment ........ 29
Figure 13 Semiconductor Device Unit Growth ............ 30
Figure 14 200 mm Fab Capacity Outlook to 2022 .......... 34
Figure 15 TECHCET Wafer Starts by Technology Node and Device Type ? 2/2019 ... 36
Figure 16 China IC Production Share and Consumption Trends ...... 37
Figure 18 IC Technology Roadmap Evolutions and Revolutions. ........ 40
Figure 19 Process and materials changes required to shrinking logic and memory devices. ... 41
Figure 20 Double patterning by increases density so called LELE for “Litho-Etch-Litho-Etch. ... 42
Figure 21 Self-aligned quadruple patterning (SAQP). ........ 43
Figure 22 Hardmask and Relationship to Pattern Collapse ....... 44
Figure 23 Dimensional scaling under pressure ........... 45
Figure 24 EPE is the difference between the intended and the printed features of an IC layout. Shrinking dimensions exacerbate EPE issues. ........ 46
Figure 33 The evolution of High-κ / Metal Gate Transistors, from planar 45 nm to the 14 nm node. ... 49
Figure 34 Comparison of CMOS Transistor used today. (A) Planar, (B) FD-SOI and (C) FinFET. ... 50
Figure 35 Possible uses for dielectrics in state of the art 10 nm FinFET Technology .... 51
Figure 36 Logic Process nodes compared. ........... 52
Figure 37 Logic Technology Industry Roadmap (TechInsight, January 2018).... 53
Figure 38 After the introduction at 22 nm by Intel a taller fin height and narrower fin width leads to more vertical profile in 14 nm and 10 nm. ........ 53
Figure 39 Leading-edge Logic Wafer Starts, historical and forecasted. ..... 54
Figure 40 Air Spacers Used Between Gates and Contacts. ......... 55
Figure 41 A Gate-all-around FET that could come into play at 5 or 3 nm..... 56
Figure 42 Imec CMOS Roadmap. .............. 57
Figure 43 Imec has achieved the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs. ............. 58
Figure 44 Three principal Cross-section simulation of (a) finFET, (b) nanowire, and (c) nanosheet. ... 59
Figure 45 TEM cross section of 5nm-node GAA-FETs by IBM, Samsung and GlobalFoundries. ... 60
Figure 46 Leti roadmap for introducing monolithic 3D Logic scaling at 5 nm... 62
Figure 47 Stacking FinFETs on FinFETs. ........... 63
Figure 48 DRAM nodes by the top 3 companies, Samsung, SK Hynix and Micron (Elpida, Nanya) compared with Winbond and the Chinese DRAM manufactures ...... 65
Figure 49 The implications of the transition to 3DNAND, less dielectrics for multiple patterning but more for the multilayer stack as well as etch hardmasks (Applied Materials).................... 67
Figure 50 Transition from 2D to 3DNAND............ 68
Figure 51 NAND Technology Roadmap. ............. 69
Figure 52 Wafer forecast for XPoint memory. ............ 70
Figure 53 Ferroelectric hafnium oxide by ALD can be integrated in 3D capacitors (FRAM) in BEOL as well as in a FEOL HKMG stack (FeFETs). ......... 71
Figure 54 An overview of emerging memory technologies that has been announced by the major players. ... 72
Figure 55 Introduction of High-κ in high volume production. ...... 73
Figure 56 Adeka yttrium precursor Y-5000. ............ 80
Figure 57 La-FMD is a promising metal-amidinate ALD precursors for lanthanum (La) based ALD thin-films which are potentially strong candidates for high-κ gate dielectric in the next generation of CMOS technology............ 82
Figure 58 TiNx grown with Brute Hydrazine at 300°C gives comparable resistivity to TiNx grown with NH3 at 400°C. ............. 83
Figure 64 Air Liquide New SAM for multiple patterning. .......... 83
Figure 65 The relative age distribution of segmented dielectric precursors filed by OEMs, chemical companies, fabricators and research organizations over the last two decades. ..................... 86
Figure 66 Distribution of dielectric precursor IP by OEMs, IDM/Foundries and Chemical Suppliers.................. 87
Figure 67 Filed IP in the field of Atomic Layer deposition. ....... 88
Figure 68 Global Filed IP in the field of Atomic Layer deposition. ...... 88
Figure 69 PEALD publications for dielectrics. .......... 89
Figure 70 Dielectric and High-κ IP Applications segmented by deposition method. ... 90
Figure 71 High-κ IP Applications segmented by metal oxide type. ........ 91
Figure 72 Cobalt IP-filing ............... 92
Figure 73 Cobalt CVD/ALD process and hardware IP. .......... 92
Figure 74 IP Applications for Cobalt chemical compounds 2011 to 2018. .... 93
Figure 77 Dielectric Precursor Market Shares by Precursor Type Estimates for 2019 & 2024. ... 95
Figure 78 Dielectric Precursor Market Forecast Estimates 2015 to 2024 (CAGR of 13%) ... 96
Figure 82 2018 WW Market Shares Dielectric Precursor Suppliers Estimate. ... 98
Figure 83 2018 Regional Market Shares - Dielectric Precursor Shipments 2018-2019... 99
Figure 91 : The copper damascene and dual damascene process for copper interconnects ... 101
Figure 92 : The fundamental differences between continuous, pulsed and atomic layer processing. ... 104
Figure 93: CVD vs. Spin on Deposition Processes. .......... 106

List of Tables

Table 1 Global GDP and Semiconductor Revenues ........ 16
Table 2 IMF World Economic Outlook .............. 20
Table 3 World Bank GDP Forecast ............. 21
Table 4 Worldwide IT Spending Forecast (Billions of U.S. Dollars)........ 23
Table 5 Smartphone Vendor Shipments (Millions of Units) ......... 24
Table 6 VLSI Research Semiconductor Revenue by Segment ...... 28
Table 7 2019 Semiconductor Equipment Outlook .......... 30
Table 8 Top IDM and Foundry Capex Spenders ............ 31
Table 9 2019 Investment Plans for Selected Device Companies ........ 32
Table 17: OEM Tool Sets for Sub-5 nm Logic devices. ......... 61
Table 18 : Critical thermal budget steps summary in a planar FDSOI integration and 3D CoolCube process for top FET in 3DVLSI. ............ 63
Table 19 Assessment of China need for advanced ALD/CVD precursors. ..... 75
Table 20 Overview of ALD OEMs supplying 200 mm tools. ......... 94
Table 21 TECHCET Market Segmentation Categories. .......... 94

 

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