 シリコンフォトニクス、LPO/LROおよびNPO/CPO：2027年～2037年の世界市場Silicon Photonics, LPO/LRO and NPO/CPO: Global Market 2027-2037 シリコンフォトニクスとは、従来の電子機器の製造と同じ製造インフラを用いて、光の生成、変調、ルーティング、検出といった光機能をシリコンチップ上に直接構築する技術である。この技術は、その歴史の大... もっと見る
サマリー シリコンフォトニクスとは、従来の電子機器の製造と同じ製造インフラを用いて、光の生成、変調、ルーティング、検出といった光機能をシリコンチップ上に直接構築する技術である。この技術は、その歴史の大部分において、効率向上――つまり、銅配線よりも高速かつ低消費電力でデータを伝送する方法――として理解されてきた。 2026年までに、その捉え方はもはや市場の実情を反映しなくなっている。人工知能（AI）やハイパフォーマンス・コンピューティング（HPC）では、チップ、サーバー、ラック間で膨大な量のデータを驚異的な速度で転送する必要があり、現在のアクセラレータ・アーキテクチャは銅製相互接続を物理的な限界まで追い込んでいる。 その結果、相互接続のボトルネックが発生し、高価で消費電力の大きいアクセラレータは、演算を行うどころか、データを待つだけで遊休状態になっている。シリコンフォトニクスは、電子ではなく光子を用いて情報を伝送する、業界の構造的な解決策となっている。光子は電子よりも高速で、距離による信号損失がはるかに少なく、チャネルあたりの情報量も多い。 光トランシーバーは、依然として業界を牽引するアプリケーションである。データ転送速度は数年ごとに倍増しており――100G、200G、400G、 800G――とデータ転送速度は数年に一度倍増しており、2026年には1.6テラビットのトランシーバーが商用化され、2027年頃には3.2Tのサンプル提供が予定され、2030年代初頭には6.4Tが登場する見込みです。 伝送速度が上昇するにつれ、光エンジンとスイッチやアクセラレータASIC間の短い銅配線さえも性能のボトルネックとなる。そのため、コパッケージド・オプティクス（CPO）やニアパッケージ・オプティクス（NPO）――光エンジンをASIC基板上に配置する技術―― が、リンクから消費電力の大きいDSPを排除するリニアドライブ・プラグガブルおよび受信光学部品（LPO/LRO）と並んで、この10年のパッケージング分野における中心的な話題となっている。 市場全体を形作っている根本的な制約があります。シリコンの間接バンドギャップにより、実用的な純シリコンレーザーを構築することは不可能です。この制約が、III-V族、ニオブ酸リチウム、窒化ケイ素、ポリマー、プラズモニクスといった相補的な材料プラットフォームや、異種集積技術のエコシステムを生み出しました。 データ通信分野以外にも、フォトニック量子コンピューティングは信頼性の高い商用セグメントへと成熟し、室温での動作とCMOSファウンドリとの互換性のおかげで、2025年には約21億米ドルの民間資本を集め、超伝導システムを凌駕することになるでしょう。 さらに、通信、FMCW LiDARおよびセンシング、ならびに生物医学用途からも需要が生まれています。 『シリコンフォトニクス、LPO/LROおよびNPO/CPO：2027-2037年の世界市場』は、2027年から2037年までの予測期間における、シリコンフォトニクスおよびフォトニック集積回路（PIC）業界に関する包括的な市場・技術評価です。 本レポートは、転換点に差し掛かっている現状を明らかにしている。銅配線の限界が露呈し、AIインフラがかつてない帯域幅を要求する中、シリコンフォトニクスは単なる効率改善から、次世代データ伝送の構造的基盤へとその役割をシフトさせている。本レポートは、市場を2つの需要の原動力―― AI主導のデータ通信と、新たに商用化されたフォトニック量子分野――を軸に市場を捉え、コパッケージド・オプティクス（CPO）、ニアパッケージ・オプティクス（NPO）、およびリニアドライブ・プラグイン型および受信用オプティクス（LPO/LRO）への移行を定量的に分析しています。 本分析では、詳細な技術解説と、セグメント別のきめ細かな予測を組み合わせています。 データ通信以外にも、本レポートでは競合および補完的なプラットフォーム、「銅の壁」とビーチフロント密度の危機、製造上の課題と東南アジアへの生産能力シフト、異なるCPOエコシステム（NVIDIA対Broadcom）とTSMCのCOUPEプラットフォーム、さらに通信、AIおよびコンピューティング、量子、 LiDARおよびセンシング、バイオメディカル、計測機器、防衛、マイクロ波フォトニクスに及ぶアプリケーション市場を網羅しています。エコシステム市場マップ、地域別分析、160社の詳細な企業プロファイルが含まれており、相互接続の変革を乗り切る投資家、チップおよびシステムベンダー、ハイパースケーラー、ファウンドリ、部品サプライヤーにとって、意思決定に役立つ参考資料となっています。 主な内容は以下の通りです：
Summary
Silicon photonics builds optical functions — the generation, modulation, routing, and detection of light — directly onto silicon chips using the same fabrication infrastructure that produces conventional electronics. For most of its history the technology was understood as an efficiency improvement: a way to move data faster and with less power than copper allows. By 2026 that framing no longer captures the market. Artificial intelligence and high-performance computing require enormous volumes of data to move at tremendous speed between chips, servers, and racks, and current accelerator architectures have pushed copper interconnect to its physical limits. The result is an interconnect bottleneck, in which expensive, power-hungry accelerators sit idle waiting for data rather than computing. Silicon photonics has become the industry's structural answer, moving information in photons rather than electrons — photons travel faster, lose far less signal over distance, and carry more information per channel. Optical transceivers remain the application that drives the industry. Data rates have doubled every few years — 100G, 200G, 400G, 800G — and 2026 saw the commercialisation of 1.6-terabit transceivers, with 3.2T expected to sample around 2027 and 6.4T following in the early 2030s. As rates climb, even the short copper trace between an optical engine and the switch or accelerator ASIC limits performance, which is why co-packaged optics (CPO) and near-package optics (NPO) — moving the optical engine onto the ASIC substrate — have become the central packaging story of the decade, alongside linear-drive pluggable and receive optics (LPO/LRO) that strip power-hungry DSP from the link.
A fundamental constraint shapes the whole market: silicon's indirect bandgap means a practical pure-silicon laser cannot be built, which has spawned an ecosystem of complementary material platforms — III-V, lithium niobate, silicon nitride, polymer, plasmonic — and heterogeneous-integration techniques. Beyond datacom, photonic quantum computing has matured into a credible commercial segment, attracting roughly US$2.1 billion in private capital in 2025 and overtaking superconducting systems, thanks to room-temperature operation and CMOS-foundry compatibility. Further demand comes from telecommunications, FMCW LiDAR and sensing, and biomedical uses.
Silicon Photonics, LPO/LRO and NPO/CPO: Global Market 2027-2037 is a comprehensive market and technology assessment of the silicon-photonics and photonic-integrated-circuit (PIC) industry across the 2027–2037 forecast period. It arrives at an inflection point: with copper interconnect exhausted and AI infrastructure demanding unprecedented bandwidth, silicon photonics has shifted from an efficiency improvement to the structural foundation of next-generation data movement. The report frames the market around its two demand engines — AI-driven data communications and the newly commercial photonic-quantum segment — and quantifies the transition to co-packaged optics (CPO), near-package optics (NPO), and linear-drive pluggable and receive optics (LPO/LRO).
The analysis pairs detailed technology explanation with granular, segmented forecasts. Beyond datacom, the report covers competing and complementary platforms, the "copper wall" and beachfront-density crisis, manufacturing challenges and the capacity shift to Southeast Asia, divergent CPO ecosystems (NVIDIA vs. Broadcom) and the TSMC COUPE platform, and application markets spanning telecommunications, AI and computing, quantum, LiDAR and sensing, biomedical, instrumentation, defence, and microwave photonics. It includes an ecosystem market map, regional analysis, and 160 detailed company profiles, making it a decision-grade reference for investors, chip and system vendors, hyperscalers, foundries, and component suppliers navigating the interconnect transition.
Content covered includes:
Table of Contents
1 PURPOSE AND SCOPE 35
2 EXECUTIVE SUMMARY 36
2.1 Market Overview 36
2.2 Electronic and Photonic Integration Compared 40
2.3 Silicon Photonic Transceiver Evolution 40
2.4 Market Map 41
2.5 Global Market Trends in Silicon Photonics 44
2.6 Competing and Complementary Photonics Technologies 45
2.6.1 Metaphotonics 48
2.6.2 III-V Photonics 48
2.6.3 Lithium Niobate Photonics 48
2.6.4 Polymer Photonics 48
2.6.5 Plasmonic Photonics 49
2.7 Potential of Photonic AI Acceleration 49
2.8 The Copper Wall and the Beachfront-Density Crisis 50
2.9 Manufacturing Capacity Shifts to Southeast Asia 50
2.10 Commercial deployment of silicon photonics 50
2.11 Co-Packaged Optics 52
2.11.1 Divergent CPO Ecosystems: NVIDIA and Broadcom 52
2.11.2 The TSMC COUPE Packaging Platform 52
2.12 Manufacturing challenges 52
2.13 The Market Opportunity 55
2.14 Regional Strengths & Research Focus 55
3 INTRODUCTION TO SILICON PHOTONICS 56
3.1 What is Silicon Photonics? 56
3.1.1 Definition and Principles of Silicon Photonics 56
3.1.2 Comparison with traditional technologies 57
3.1.3 Silicon and Photonic Integrated Circuits 60
3.1.4 Optical IO, Coupling and Couplers 63
3.1.5 Emission and Photon Sources/Lasers 64
3.1.6 Detection and Photodetectors 64
3.1.7 Compound Semiconductor Lasers and Photodetectors (III-V) 65
3.1.8 Modulation, Modulators, and Mach-Zehnder Interferometers 66
3.1.8.1 New modulator technologies 67
3.1.9 Light Propagation and Waveguides 68
3.1.10 Optical Component Density 69
3.2 Advantages of Silicon Photonics 70
3.3 Applications of Silicon Photonics 70
3.4 Comparison with Other Photonic Integration Technologies 71
3.5 Evolution from Electronic to Photonic Integration 72
3.6 Silicon Photonics vs Traditional Electronics 73
3.7 Modern high-performance AI data centers 74
3.8 Core Technology Components 77
3.8.1 Optical IO, Coupling and Couplers 77
3.8.2 Emission and Photon Sources/Lasers 78
3.8.2.1 III-V Integration Challenges 79
3.8.2.2 Laser Integration Approaches 79
3.8.3 Detection and Photodetectors 80
3.8.4 Modulation Technologies 80
3.8.4.1 Mach-Zehnder Interferometers 81
3.8.4.2 Ring Modulators 81
3.8.4.3 Micro-Ring Modulators as a Competitive Differentiator 82
3.8.5 Light Propagation and Waveguides 82
3.8.6 Optical Component Density 82
3.9 Basic Optical Data Transmission 84
4 MATERIALS AND COMPONENTS 86
4.1 Silicon 86
4.1.1 Silicon as a Photonic Material 86
4.1.1.1 Optical Properties of Silicon 87
4.1.1.2 Fabrication Processes for Silicon Photonics 87
4.1.2 Silicon-on-insulator (SOI) 88
4.1.2.1 SOI Manufacturing Process 92
4.1.2.2 Key SOI Players 95
4.2 Germanium 96
4.2.1 Germanium Integration in Silicon Photonics 96
4.2.2 Germanium Photodetectors 96
4.2.3 Germanium-on-Silicon Modulators 97
4.3 Silicon Nitride 97
4.3.1 Silicon Nitride (SiN) in Photonics Integrated Circuits 97
4.3.2 Optical Properties and Fabrication of SiN 99
4.3.3 SiN Modulator Technologies 99
4.3.4 SiN Applications in Photonics Integrated Circuits 100
4.3.5 Advances in SiN Modulator Technologies 101
4.3.6 SiN-based Waveguides and Devices 101
4.3.7 SiN Performance Analysis 102
4.3.8 Applications of SiN in Photonics 103
4.3.9 SiN PIC Players 103
4.3.10 SiN Key Foundries 106
4.4 Thin Film Lithium Niobate (TFLN) 109
4.4.1 Overview 109
4.4.2 Lithium Niobate on Insulator (LNOI) 110
4.4.2.1 Overview of LNOI Technology 110
4.4.2.2 Characteristics and Properties of LNOI 111
4.4.2.3 LNOI Fabrication Processes 111
4.4.2.4 LNOI-based Modulator and Switch Technologies 112
4.4.2.5 Trends Toward Higher Speed and Improved Power Efficiency 112
4.4.2.6 High-Speed LNOI Modulators 113
4.4.2.6.1 Energy-Efficient LNOI Devices 114
4.4.2.6.2 Emerging LNOI Device Technologies 114
4.5 Indium Phosphide 115
4.5.1 Indium Phosphide (InP) Integration 115
4.5.1.1 InP as a Direct Bandgap Semiconductor 115
4.5.1.2 InP-based Active Components 116
4.5.1.3 Hybrid Integration of InP with Silicon Photonics 116
4.5.2 InP PIC Players 116
4.6 Barium Titanite and Rare Earth metals 117
4.6.1 Barium Titanate (BTO) Modulators 118
4.7 Organic Polymer on Silicon 119
4.7.1 Polymer-based Modulators 120
4.8 Wafer Processing 120
4.8.1 Wafer Sizes by Platform 120
4.8.2 Processing Challenges 121
4.8.3 Yield Management 121
4.9 Hybrid and Heterogeneous Integration 122
4.9.1 Monolithic Integration 122
4.9.2 Hybrid Integration 123
4.9.3 Heterogeneous Integration 123
4.9.4 III-V-on-Silicon 123
4.9.5 Bonding and Die-Attachment Techniques 123
4.9.6 Monolithic versus Hybrid Integration 124
5 ADVANCED PACKAGING TECHNOLOGIES 126
5.1 Evolution of Packaging Technologies 126
5.1.1 Traditional Packaging Approaches 129
5.1.2 Advanced Packaging Roadmap 130
5.1.3 Key Performance Metrics 132
5.2 2.5D Integration Technologies 133
5.2.1 Silicon Interposer Technology 134
5.2.2 Organic Substrate Options 136
5.3 3D Integration Approaches 136
5.3.1 Through-Silicon Via (TSV) 137
5.3.1.1 TSV Manufacturing Process 138
5.3.1.2 TSV Challenges and Solutions 139
5.3.2 Hybrid Bonding Technologies 140
5.3.2.1 Cu-Cu Bonding 141
5.3.2.2 Direct Bonding 141
5.4 Co-Packaged Optics (CPO) 142
5.4.1 CPO Architecture Overview 142
5.4.2 Benefits and Challenges 142
5.4.3 Integration Approaches 144
5.4.3.1 2D Integration 144
5.4.3.2 2.5D Integration 145
5.4.3.3 3D Integration 145
5.4.4 Thermal Management 146
5.4.5 Optical Coupling Solutions 146
5.5 Optical Alignment 147
5.5.1 Active vs Passive Alignment 147
5.5.2 Coupling Efficiency 148
5.6 Manufacturing Challenges 148
6 OPTICAL INTERCONNECT ARCHITECTURES FOR AI: PLUGGABLES, LPO/LRO, NPO AND CPO 151
6.1 The Rise and Challenges of Large Language Models (LLMs) 151
6.1.1 The Explosive Growth of AI and Generative AI 151
6.1.1.1 Historical Context and Acceleration 151
6.1.1.2 Compute Demand Scaling 151
6.1.1.3 Generative AI Market Expansion 151
6.1.2 Modern High-Performance AI Data Centre Requirements 154
6.1.2.1 Compute Density Requirements 154
6.1.2.2 Network Topology Requirements 154
6.1.2.3 Availability and Reliability Requirements 154
6.1.3 NVIDIA’s State-of-the-Art AI Systems 155
6.1.3.1 DGX H100 and HGX H100 155
6.1.3.2 Blackwell and Rubin Architectures 156
6.1.4 Switches: Key Components in Modern Data Centres 157
6.1.4.1 Switch Hierarchy in AI Data Centres 157
6.2 Scale-Up, Scale-Out, and Scale-Across Networks 159
6.2.1 Scale-Up Networks: GPU-to-GPU Interconnects 159
6.2.1.1 NVIDIA NVLink Implementation 159
6.2.2 Scale-Out Networks: Rack-to-Rack Communications 160
6.2.2.1 Ethernet-Based Scale-Out 160
6.2.2.2 InfiniBand for AI 161
6.2.2.3 CPO Value Proposition for Scale-Out 161
6.2.3 Scale-Up, Scale-Out, and Scale-Across Comparison 162
6.2.4 Roadmap of Interconnect Technology for Network Switches in High-End Data Centres 163
6.2.4.1 Technology Generations 163
6.2.5 SerDes Bottleneck in High-Bandwidth Systems 165
6.2.5.1 SerDes Function 165
6.2.5.2 Channel Loss Challenges 166
6.2.6 Solutions to SerDes Bottlenecks in High-Bandwidth Systems 166
6.2.6.1 Linear-Drive Electronics 166
6.2.6.2 Near-Package Optics 166
6.2.6.3 Co-Packaged Optics 167
6.2.7 Pluggable Optics: Current Bottlenecks and Limitations 167
6.2.7.1 Form Factor Constraints 167
6.2.7.2 Electrical Interface Limitations 167
6.2.8 On-Board Optics (OBO) 168
6.2.8.1 CPO Architecture 170
6.2.8.2 Key Enabling Technologies 170
6.2.8.3 Performance Benefits 171
6.2.8.4 Implementation Challenges 171
6.2.9 Transmission Losses in Pluggable Optical Transceiver Connections 171
6.2.10 Pluggable Optics vs. CPO 172
6.2.11 Design Decisions for CPO Compared to Pluggables 173
6.2.12 Advancements in Switch IC Bandwidth and the Need for CPO Technology 174
6.2.12.1 Bandwidth Scaling Trajectory 174
6.2.13 L2 Frontside Network Architecture Diagram: CPO vs. Non-CPO 176
6.3 Challenges in Compute Switch Interconnects (Optical I/O) for High-End Data Centres 178
6.3.1 Number of Copper Wires in Current AI System Interconnects 178
6.3.1.1 NVLink Copper Cable Count 178
6.3.2 Limitations of Current Copper Systems in AI 180
6.3.3 NVIDIA’s Connectivity Choices: Copper vs. Optical for High-Bandwidth Systems 181
6.3.3.1 Current Generation: Copper-Centric 181
6.3.3.2 Future Generation: Optical-First 181
6.3.4 Strategic Implications 182
6.3.5 Copper vs. Optical for High-Bandwidth Systems: Benchmark 182
6.3.6 Migration from Copper to Optical Interconnects for High-End AI Systems 182
6.3.7 Current AI System Architecture 185
6.3.8 L1 Backside Compute Architecture with Copper Systems 186
6.3.9 L1 Backside Compute Architecture with Optical Interconnect: Co-Packaged Optics (CPO) 186
6.4 Future AI Systems in High-End Data Centres 188
6.4.1 Power Efficiency Comparison: CPO vs. Pluggable Optics vs. Copper Interconnects 188
6.4.1.1 Power Consumption Breakdown 188
6.4.2 Latency of 60cm Data Transmission Technology Benchmark 190
6.4.3 Future AI Architecture (Short to Mid-Term) 190
6.4.4 Future AI Architecture (Long-Term) 193
7 CO-PACKAGED OPTICS (CPO) 197
7.1 Photonic Integrated Circuits (PICs) Key Concepts 197
7.1.1 What are Photonic Integrated Circuits (PICs)? 197
7.1.1.1 Fundamental Definition 197
7.1.1.2 Material Platforms 197
7.1.1.3 Integration Levels 197
7.1.2 PICs vs. Silicon Photonics: What are the Differences? 199
7.1.2.1 Silicon Photonics: A Specific Implementation 199
7.1.2.2 Why Silicon Photonics Dominates CPO 199
7.1.3 PIC Architecture 201
7.1.3.1 Transmit Path Architecture 201
7.1.3.2 Receive Path Architecture 201
7.1.3.3 Supporting Functions 202
7.1.3.4 Advantages and Challenges of PICs 202
7.2 Optical Engine (OE) 204
7.2.1 What is an Optical Engine? 204
7.2.1.1 Optical Engine Composition 204
7.2.1.2 Optical Engine vs. Pluggable Transceiver 204
7.2.2 How an Optical Engine Works 205
7.2.2.1 Transmit Path Operation 205
7.2.2.2 Receive Path Operation 205
7.2.2.3 Critical Performance Parameters 206
7.2.3 Optical Power Supplies 206
7.2.3.1 Why External Laser Sources? 206
7.2.3.2 External Laser Source Architectures 207
7.2.3.3 Optical Power Delivery 207
7.3 Three Key Concepts in Co-Packaged Optics (CPO) 207
7.3.1 Concept 1: Proximity Integration 207
7.3.2 Concept 2: Functional Partitioning 208
7.3.3 Concept 3: Coherent Ecosystem Development 208
7.3.4 Key Technology Building Blocks for CPO 209
7.3.4.1 Silicon Photonics PIC 209
7.3.4.2 Electronic IC (EIC) 210
7.3.4.3 EIC-PIC Integration 210
7.3.4.4 Fibre Array Units (FAUs) 210
7.3.4.5 External Laser Source 210
7.3.4.6 Advanced Packaging Platform 210
7.3.5 Benefits of CPO: Latency Reduction 213
7.3.5.1 Sources of Latency in Optical Interconnects 213
7.3.5.2 CPO Latency Advantages 213
7.3.6 Benefits of CPO: Power Consumption Reduction 214
7.3.6.1 Power Consumption Breakdown 214
7.3.6.2 Why CPO Consumes Less Power 214
7.3.7 Benefits of CPO: Data Rate Improvements 216
7.3.7.1 Pluggable Scaling Limitations 216
7.3.7.2 CPO Scaling Advantages 216
7.3.7.3 Data Rate Scaling Roadmap 216
7.3.7.4 The 200G-per-Lane Transition and Silicon Photonics 217
7.3.7.5 Modulator Technology Roadmap and Emerging Materials 217
7.3.7.6 Technology Trends in CPO Driven by Rising Data Rates 217
7.3.7.7 Applicability of Wavelength-Division Multiplexing (WDM) 219
7.3.7.8 Physical Limits on Fibre Count: The Beachfront (Shoreline) Constraint 220
7.3.7.9 Increasing the Number of WDM Channels: Technical Challenges 220
7.3.7.10 The End-to-End Optical Link Budget 221
7.3.8 Overview of Value Proposition of CPO 222
7.3.8.1 Value for Hyperscale Data Centre Operators 222
7.3.8.2 Value for Network Equipment Vendors 222
7.3.8.3 Value for the Technology Ecosystem 222
7.3.9 Future Challenges in CPO 223
7.3.9.1 Manufacturing and Yield Challenges 223
7.3.9.2 Thermal Management Challenges 223
7.3.9.3 Serviceability and Reliability Challenges 223
7.3.9.4 Ecosystem and Standardisation Challenges 224
7.3.9.5 Cost Challenges 224
7.3.9.6 Test and Manufacturing Scale-Up 224
7.4 CPO Standards 225
7.4.1 OIF Co-Packaging Framework 226
7.4.2 OCI-MSA (Optical Compute Interconnect Multi-Source Agreement) 227
7.4.3 OIF Standards for 1.6T and 3.2T CPO Module 227
7.4.4 External Laser Small Form Pluggable (ELSFP) Implementation Agreement 228
7.4.5 Telemetry and Management 229
7.4.6 OIF’s CEI-112G XSR / XSR+ PAM4 229
7.4.7 UCIe Standard and Its Relationship to CPO 230
7.4.8 XPO and Open CPX Initiatives 232
7.4.9 Near-Package Optics (NPO) as an Intermediate Path 232
8 CO-PACKAGED OPTICS MARKET ANALYSIS 233
8.1 CPO Market Definition and Scope 233
8.2 CPO Market Size and Growth Projections 233
8.3 Switch CPO Market Analysis 234
8.3.1 Market Overview and Drivers 234
8.3.2 Deployment Timeline and Adoption Phases 234
8.3.3 Volume Projections and Market Sizing 235
8.3.4 Market Concentration and Regional Distribution 236
8.3.5 Pricing Trajectory and Cost Dynamics 236
8.4 XPU Optical I/O Market Analysis 237
8.4.1 Market Drivers and Value Proposition 237
8.4.2 Adoption Timeline and Platform Evolution 237
8.4.3 Volume and Revenue Projections 238
8.4.4 Market Segmentation by Platform 239
8.4.5 Technology Requirements and Differentiation 239
8.5 CPO Pricing and Cost Analysis 240
8.5.1 Current Pricing Landscape 240
8.5.2 Cost Trajectory and Reduction Drivers 240
8.5.3 Cost Parity Timeline and Dynamics 241
8.5.4 Pricing Strategy Implications 242
8.6 Regional Market Dynamics 243
8.6.1 North America 243
8.6.2 Asia-Pacific 244
8.6.3 Europe 245
8.6.4 Rest of World 246
8.7 Total Addressable Market Analysis 247
8.7.1 Core TAM Segments 247
8.7.2 Serviceable Addressable Market (SAM) 248
8.8 Market Forecast by Component 249
8.9 Market Forecast by Technology Generation 250
8.9.1 Optical Engine Bandwidth Evolution 250
8.9.2 Generation Lifecycle Analysis 251
8.10 Market Restraints and Barriers 252
8.10.1 Manufacturing Yield and Cost 252
8.10.2 Serviceability and Field Replacement Concerns 253
8.10.3 Standards Maturity and Interoperability 253
8.10.4 Supply Chain Capacity Constraints 254
8.10.5 Competitive Alternatives 255
8.11 Adoption Curve Analysis 256
8.11.1 Technology Adoption Framework 256
8.11.1.1 Innovators (2024-2026) 256
8.11.1.2 Early Adopters (2026-2028) 257
8.11.1.3 Early Majority (2028-2031) 258
8.11.1.4 Laggards (2034+) 259
8.11.2 Segment-Specific Adoption Curves 260
8.12 Adoption Accelerators and Inhibitors 261
8.12.1 Adoption Curve Implications 261
8.13 Competitive Landscape Evolution 262
8.13.1 Current Competitive Positioning 262
8.13.2 Integrated Device Manufacturers (IDMs) 262
8.13.3 Silicon Photonics Specialists 262
8.13.4 Foundry/OSAT Providers 262
8.13.5 System Vendors 263
8.13.6 Laser Suppliers 263
8.13.7 Competitive Dynamics and Market Structure Evolution 264
8.13.7.1 Near-Term Dynamics (2025-2028) 264
8.13.7.2 Expected Evolution (2028) 264
8.13.7.3 Mid-Term Dynamics (2028-2032) 264
8.13.7.3.1 Expected Evolution (2032) 265
8.13.7.4 Long-Term Dynamics (2032-2037) 265
8.13.7.4.1 Expected Evolution (2037) 265
8.13.8 Vertical Integration Trends 266
8.13.8.1 Integration Strategy Framework 266
8.13.8.1.1 Full Vertical Integration 266
8.13.8.1.2 Partial Integration 266
8.13.8.1.3 Fabless/Assembly-Light 267
8.13.8.1.4 Platform Provider 267
8.13.8.2 Strategic Implications of Integration Trends 269
8.13.9 Recent Developments — Q1 2026 269
8.13.10 Recent Developments — Q2 2026 270
8.14 Scenario Analysis 271
8.14.1 Scenario Framework 271
8.14.2 Scenario Definitions 271
8.14.3 Bull Case Scenario 272
8.14.4 Base Case Scenario 272
8.14.5 Bear Case Scenario 273
8.14.6 Optical transceiver market 274
8.14.7 Scenario Comparison and Key Variables 274
9 GLOBAL MARKET SIZE AND FORECASTS 2027–2037 276
9.1 Headline Market Model 2027–2037 276
9.2 Market Segmentation by Application 2027–2037 276
9.3 Market Segmentation by Interconnect Architecture 2027–2037 277
9.4 Modules and PIC Dies 2027–2037 277
9.4.1 Global Silicon Photonics and Photonic Integrated Circuits Market Overview 278
9.4.1.1 Market Size and Growth Trends 278
9.4.1.2 Market Segmentation by Application 278
9.4.1.3 Server Boards, CPUs and Accelerators 279
9.4.1.4 Modules & PICs (Dies) Market Forecast 2027–2037 279
9.4.1.5 SOI Wafers for Silicon Photonics 280
9.4.1.6 LPO & New Modulator Materials Market Forecast 2027–2037 280
9.4.2 Datacom Applications 281
9.4.2.1 Market Forecast 281
9.4.2.1.1 Datacom and Telecom Modules and PICs 281
9.4.2.1.2 PIC Transceivers for AI 282
9.4.2.1.3 PIC Transceiver Pricing 282
9.4.2.2 PIC Transceiver Cost per Gigabit 283
9.4.2.3 PIC Datacom Transceiver Market 283
9.4.2.4 Datacom Transceiver Revenue by Customer Type 284
9.5 Quantum PIC Market 284
9.5.1. Key Drivers and Restraints 285
9.5.2 Co-Packaged Optics 285
9.5.3 Telecom Applications 286
9.5.3.1 Market Forecast 286
9.5.3.1.1 PIC-based Transceivers for 5G and 6G 286
9.5.3.2 Key Drivers and Restraints 287
9.5.4 Sensing Applications 287
9.5.4.1 Market Forecast 287
9.5.4.2 Key Drivers and Restraints 288
9.5.5 Photonic Integrated Circuit Market, by Material 289
10 SUPPLY CHAIN, TECHNOLOGY TRENDS AND FUTURE CHALLENGES 290
10.1 SUPPLY CHAIN ANALYSIS 290
10.1.1 Foundries and Wafer Suppliers 291
10.1.1.1 CMOS Foundries 291
10.1.1.2 Specialty Photonics Foundries 292
10.1.1.3 Indium Phosphide Wafer Supply 293
10.1.2 Integrated Device Manufacturers (IDMs) 294
10.1.2.1 Fabless Companies 294
10.1.2.2 Fully Integrated Photonics Companies 295
10.1.3 Foundries and Wafer Suppliers 296
10.1.4 Packaging and Testing 297
10.1.4.1 Chip-Scale Packaging 297
10.1.4.2 Module-Level Packaging 297
10.1.4.3 Testing and Characterization 297
10.1.4.4 Optical Module Assembly: The Shift to Southeast Asia 298
10.1.4.5 The EML Laser Shortage 298
10.1.5 System Integrators and End-Users 299
10.1.5.1 CPO Partner Ecosystems: NVIDIA and Broadco 300
10.2 TECHNOLOGY TRENDS 301
10.2.1 Laser Integration Techniques 301
10.2.1.1 Direct Epitaxial Growth 301
10.2.1.2 Flip-Chip Bonding 302
10.2.1.3 Hybrid Integration 302
10.2.1.4 Advances and Challenges 303
10.2.2 Modulator Technologies 304
10.2.2.1 Silicon Modulators 304
10.2.2.2 Germanium Modulators 305
10.2.2.3 Lithium Niobate Modulators 305
10.2.2.4 Polymer Modulators 305
10.2.2.4.1 Tower Semiconductor and Lightwave Logic EO-Polymer 306
10.2.3 Photodetector Technologies 306
10.2.3.1 Silicon Photodetectors 306
10.2.3.2 Germanium Photodetectors 307
10.2.3.3 III-V Photodetectors 307
10.2.4 Waveguide and Coupling Innovations 307
10.2.4.1 Silicon Waveguides 307
10.2.4.2 Silicon Nitride Waveguides 308
10.2.4.3 Coupling Techniques 308
10.2.5 Packaging and Integration Advancements 308
10.2.5.1 Chip-Scale Packaging 308
10.2.6 Wafer-Scale Integration 309
10.2.6.1 3D Integration and Interposer Technologies 309
10.3 CHALLENGES AND FUTURE TRENDS 310
10.3.1 CMOS-Foundry-Compatible Devices and Integration 310
10.3.1.1 Scaling and Miniaturization 311
10.3.1.2 Process Complexity and Yield Improvement 311
10.3.1.3 Energy-Efficient Photonic Devices 313
10.3.1.4 Thermal Optimization Techniques 313
10.3.2 Packaging and Testing 314
10.3.2.1 Advanced Packaging Solutions 314
10.3.2.2 Automated Testing and Characterization 315
10.3.3 Scalability and Cost-Effectiveness 315
10.3.3.1 Wafer-Scale Integration 316
10.3.3.2 Outsourced Semiconductor Assembly and Test (OSAT) 317
10.3.4 Emerging Materials and Hybrid Integration 317
10.3.4.1 Novel Semiconductor Materials 318
10.3.4.2 Heterogeneous Integration Approaches 318
10.3.5 Technology Readiness Assessment 319
11 COMPANY PROFILES 322 (160 company profiles)
12 REFERENCES 491
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