The advanced semiconductor packaging market is experiencing rapid growth, driven by technological demands that are pushing the industry beyond traditional Moore's Law scaling.  The market's growth is underpinned by the increasing importance of packaging technologies in addressing computing demands. The telecom and infrastructure sector currently dominates the market, and the mobile and consumer segment is emerging as the fastest-growing market.

 

3D stack memory technologies—including HBM, 3DS, 3D NAND, and CBA DRAM—are key growth drivers. The fastest-growing platforms include CBA DRAM, 3D SoC, active silicon interposers, 3D NAND stacks, and embedded silicon bridges. These technologies are critical for meeting the increasing performance, power, and miniaturization demands of modern electronics.

 

Heterogeneous integration and chiplet-based designs are revolutionizing semiconductor architecture. Major industry players like TSMC, Intel, AMD, and Nvidia are heavily investing in advanced packaging solutions to overcome the limitations of traditional monolithic chip designs. The adoption of hybrid bonding technologies is particularly transformative, enabling finer interconnect pitches and higher integration densities. The competitive landscape is evolving as foundries, IDMs, and OSATs vie for market share. In 2024, memory players including YMTC, Samsung, SK Hynix, and Micron. Top OSATs like ASE, SPIL, JCET, Amkor, and TF continue to provide assembly and test services while developing their high-end packaging capabilities through UHD FO and mold interposer technologies.

 

Looking toward 2035, several trends will shape the market. The integration of chiplets using 3D SoC, 2.5D interposers, embedded silicon bridges, and co-packaged optics will create increasingly complex "3.5D" packages. Panel-level packaging is gaining traction for larger packages, offering cost advantages over wafer-level processes. Simultaneously, the industry is transitioning from micro-bump technology to bumpless hybrid bonding, enabling finer interconnect pitches necessary for advanced nodes. By application, high-performance computing, AI accelerators, data centers, and autonomous vehicles represent the fastest-growing segments. The rise of AI and cloud computing is driving demand for advanced memory packaging solutions like HBM and specialized processors requiring sophisticated heterogeneous integration.

 

Further consolidation among suppliers is likely, with foundries and IDMs strengthening their packaging capabilities. The emergence of new players from regions like China will intensify competition, while the importance of equipment suppliers like BESI, Applied Materials, and EVG will grow with the adoption of cutting-edge bonding technologies.

 

The Global Advanced Semiconductor Packaging Market 2025-2035 provides a comprehensive analysis of the rapidly evolving advanced semiconductor packaging industry, examining how technological innovations are reshaping the semiconductor landscape beyond traditional Moore's Law scaling.

 

Report Contents include:

• Market Size and Growth Projections: Detailed forecasts of the advanced semiconductor packaging market from 2025 to 2035, with comprehensive breakdowns by packaging type, units and wafers, end-use markets, and geographical regions.
• Technology Evolution Analysis: In-depth examination of the transition from 1D to 3D packaging architectures, including technology roadmaps for interconnect density, reticle size considerations, and the shifting value balance between front-end and back-end processes.

Packaging Technology Deep Dives

• Wafer Level Packaging (WLP) and Fan-Out techniques
• 2.5D and 3D packaging architectures
• Silicon, organic, and glass-based interposer technologies
• Through-silicon via (TSV) implementation strategies
• Hybrid bonding and copper-to-copper interconnect innovations
• Panel Level Packaging (PLP) advancements and scaling benefits

Emerging Technology Assessments

• Chiplet ecosystem development and standardization efforts
• System-in-Package (SiP) integration approaches
• Co-Packaged Optics (CPO) implementations
• Monolithic 3D integration pathways
• Advanced IC substrate technologies

Market Segmentation Analysis: Detailed examination of packaging requirements, challenges, and solutions across key application segments

• High Performance Computing and AI accelerators
• Data center infrastructure
• Mobile devices and consumer electronics
• Automotive electronics and autonomous systems
• IoT and edge computing devices
• 5G/6G communication infrastructure
• Aerospace and defense applications
• Medical electronics

Competitive Landscape: Comprehensive profiles of 128+ companies spanning the entire advanced packaging ecosystem, including

• Integrated Device Manufacturers (IDMs)
• Outsourced Semiconductor Assembly and Test (OSAT) providers
• Foundries and semiconductor manufacturing leaders
• Equipment and materials suppliers
• Electronics OEMs driving packaging innovation. Companies profiled include AaltoSemi, Absolic, ACCRETECH, Adeia, Advanced Micro Devices (AMD), Amkor Technology, Anmuquan Intelligent Technology, Apple, Applied Materials, Ardentec, ARM, ASE, ASMPT, Besi, Biren Technology, Blue Ocean Smart System, Brewer Science, Broadcom, BroadPak, Cambricon Technologies, Capcon Semiconductor, CAS Microelectronics Integration, CD Micro-Technology, CEA-Leti, Cerebras, China Wafer Level CSP, Chipbond Technology, Chipletz, ChipMOS Technologies, Corning, Dewo Advanced Automation, Disco, Dupont, Ebara, Eliyan, EMC Semi-Conductor Technology, Entegris, EPS Technology, EV Group, GlobalFoundries, Global Unichip, Gloway, Goldenscope Tech, Gona Semiconductor Technology, Graphcore, Greatek Electronics, Hangke Chuangxing, Hanmi Semiconductor, HiSilicon, HLMC, Huatian Huichuang Technology, Huawei, Ibiden, IBM, ICLeague Technology, IMEC, Infineon Technologies, Integra, Inari Amertron Berhad, Intel, JCET Group, Jiangsu IC Assembly & Test, Jingdu Semiconductor, Keyang Semiconductor, King Yuan Electronics, Kioxia, KyLitho, Kyocera, Lam Research, Lapis Technology, LB Semicon, Leading Interconnect Semiconductor Technology, Lidrotec, Lux Semiconductors, Malaysian Pacific Industries Berhad, MediaTek, Micron Technology, Micross Components, Mitsubishi, National Center For Advanced Packaging China, NEC, Nepes Corporation, Nvidia, Onsemi, Orient Semiconductor Electronics, Panasonic, Powertech Technology, Pragmatic Semiconductor, Qorvo, Renesas and more....

Product Analysis: Detailed examination of commercialized advanced packaging implementations in leading-edge products

• GPU architectures (Nvidia Hopper/Blackwell, AMD Instinct, Intel)
• AI accelerators (Google TPU, Amazon Trainium/Inferentia, Microsoft Maia)
• Advanced CPUs (AMD Ryzen/EPYC, Intel Meteor Lake/Arrow Lake, AWS Graviton)
• Memory technologies (HBM, 3D NAND, CBA DRAM)

・Supply Chain Dynamics: Analysis of the evolving advanced packaging supply chain, including the shifting relationships between IDMs, foundries, OSATs, and materials/equipment providers.

1.1 Semiconductor Packaging Technology Overview  19

1.1.1  Key challenges 20

1.1.2  Evolution of semiconductor packaging 21

1.1.2.1 From 1D to 3D 22

1.1.3  Conventional packaging approaches  24

1.1.4  Advanced packaging approaches  24

1.2 Semiconductor Supply Chain  26

1.3 Advanced Packaging Supply Chain 26

1.4 Key Technology Trends in Advanced Packaging 27

1.5 Market Growth Drivers  28

1.6 Competitive Landscape  28

1.7 Market Challenges 29

1.8 Future outlook 30

1.8.1  Heterogeneous Integration  30

1.8.2  Chiplets and Die Disaggregation 31

1.8.3  Advanced Interconnects 32

1.8.4  Scaling and Miniaturization 32

1.8.5  Thermal Management  33

1.8.6  Materials Innovation 33

1.8.7  Supply Chain Developments 34

1.8.8  Role of Simulation and Data Analytics 34

 

 

2.1 Transistor Device Scaling 35

2.1.1  Overview 35

2.1.2  Heterogeneous Architecture Transition 36

2.1.3  Co-Design Focus Areas 36

2.2 Wafer Level Packaging  38

2.3 Fan-Out Wafer Level Packaging 40

2.4 Chiplets  41

2.4.1  AMD EPYC and Ryzen processor families  43

2.4.2  Disaggregation Needs 44

2.5 Interconnection in Semiconductor Packaging 44

2.5.1  Overview 45

2.5.2  Wire Bonding 46

2.5.3  Flip-chip bonding 46

2.5.4  Interposer  47

2.5.4.1 Glass interposer 48

2.5.5  Through-silicon via (TSV) bonding  48

2.5.6  Hybrid bonding with chiplets 48

2.6 2.5D and 3D Packaging 49

2.6.1  2.5D packaging  49

2.6.1.1 Overview 49

2.6.1.1.1 Silicon Interposer 2.5D 50

2.6.1.1.1.1 Through Si Via (TSV)  51

2.6.1.1.1.2 (SiO2) based redistribution layers (RDLs)  52

2.6.1.1.2 2.5D Organic-based packaging  53

2.6.1.1.2.1 Chip-first and chip-last fan-out packaging 54

2.6.1.1.2.2 Organic substrates 55

2.6.1.1.2.3 Organic RDL  56

2.6.1.1.3 2.5D glass-based packaging 57

2.6.1.1.3.1 Benefits  58

2.6.1.1.3.2 Glass Si interposers in advanced packaging  59

2.6.1.1.3.3 Glass material properties 59

2.6.1.1.3.4 2/2 μm line/space metal pitch on glass substrates 60

2.6.1.1.3.5 3D Glass Panel Embedding (GPE) packaging 61

2.6.1.1.3.6 Thermal management  63

2.6.1.1.3.7 Polymer dielectric films 63

2.6.1.1.3.8 Challenges 63

2.6.1.1.3.9 Comparison with other substrates 64

2.6.1.1.4 2.5D vs. 3D Packaging  65

2.6.1.2 Benefits  66

2.6.1.3 Challenges 66

2.6.1.4 Trends 66

2.6.1.5 Market players 67

2.6.2  3D packaging 67

2.6.2.1 Overview 69

2.6.2.1.1 Conventional 3D packaging 69

2.6.2.1.2 Advanced 3D Packaging with through-silicon vias (TSVs) 70

2.6.2.1.3 Three-dimensional (3D) hybrid bonding 71

2.6.2.1.3.1 Devices using hybrid bonding  71

2.6.2.2 3D Microbump technology  72

2.6.2.2.1 Technologies 73

2.6.2.2.2 Challenges 74

2.6.2.2.3 Bumpless copper-to-copper (Cu-Cu) hybrid bonding 74

2.6.2.3 Trends 75

2.6.2.3.1 3D interconnect trends 77

2.6.2.4 Hybrid Bond and Fusion Bond  78

 

 

3.1 Introduction  79

3.1.1  WLP to PLP 79

3.2 Benefits  79

3.3 Types of Wafer Level Packaging 80

3.3.1  Wafer Level Chip Scale Packaging 81

3.3.1.1 Overview 81

3.3.1.2 Advantages 81

3.3.1.3 Applications  82

3.3.2  Wafer Level Fan-Out Packaging 82

3.3.2.1 Overview 82

3.3.2.2 Advantages 83

3.3.2.3 Applications  84

3.3.3  Wafer Level Fan-In Packaging  85

3.3.3.1 Overview 85

3.3.3.2 Advantages 85

3.3.3.3 Applications  86

3.3.4  Other Types of WLP  86

3.3.4.1 Cu-Pillar Flip Chip 86

3.3.4.2 Advantages 86

3.3.4.2.1 Applications  87

3.3.4.3 Embedded Wafer Level BGA (eWLB) 87

3.3.4.4 Advantages 88

3.3.4.4.1 Applications  89

3.3.4.5 Chip-last FO-WLP 89

3.3.4.5.1 Advantages 89

3.3.4.5.2 Applications  90

3.3.4.6 Wafer-on-Wafer (WoW) 91

3.3.4.6.1 Applications  91

3.4 WLP Manufacturing Processes 92

3.4.1  Wafer Preparation 92

3.4.2  RDL Buildup  93

3.4.3  Bumping 93

3.4.4  Encapsulation 93

3.4.5  Integration 94

3.4.6  Test and Singulation 94

3.5 Wafer Level Packaging Trends  95

3.6 Applications of Wafer Level Packaging  96

3.6.1  Mobile and Consumer Electronics 96

3.6.2  Automotive Electronics 96

3.6.3  IoT and Industrial  96

3.6.4  High Performance Computing  97

3.6.5  Aerospace and Defense  97

3.7 Wafer Level Packaging Outlook  97

 

 

4.1 Introduction  99

4.2 Approaches for heterogenous integration 100

4.2.1  Technology Building Blocks 100

4.3 SiP Manufacturing Approaches  101

4.3.1  2.5D Integrated Interposers 102

4.3.2  Multi-Chip Modules  102

4.3.3  3D Stacked packages 103

4.3.4  Fan-Out Wafer Level Packaging 103

4.3.5  Flip Chip Package-on-Package 103

4.4 SiP Component Integration 104

4.5 Heterogeneous Integration Drivers 104

4.6 Trends Driving SiP Adoption 105

4.7 SiP Applications 107

4.8 SiP Industry Landscape 107

4.9 Future Outlook on Heterogeneous Integration 108

4.10 CPO (Co-Packaged Optics) 110

4.10.1 Co-packaging approaches  110

4.10.2 Heterogeneous integration of EIC and PIC 111

4.10.3 Advantages and limitations 112

4.11 IC Substrates 113

 

 

5.1 Overview 114

5.1.1  Transitioning from 2D Systems 114

5.1.2  Motivation for developing monolithic 3D manufacturing 114

5.1.3  Improved M3D Interconnect Density 114

5.1.4  Heterogenous 3D vs Monolithic 3D 116

5.1.5  2D Materials  116

5.2 Benefits  117

5.3 Challenges 118

5.4 Future outlook 118

 

 

6.1 Market value chain 120

6.1.1  SiP OEM/Designers  121

6.1.2  Chiplet OEM/Designer and Chiplet Foundry  121

6.1.3  Chiplet Integrator 122

6.1.3.1 Integrated Device Manufacturers (IDMs) 122

6.1.3.2 Outsourced Semiconductor Assembly and Test (OSAT) Providers  122

6.1.4  Material Suppliers 122

6.1.5  Equipment Suppliers 122

6.1.6  Substrate and PCB suppliers 122

6.1.7  EDA Tools Suppliers  123

6.1.8  Interposer Foundry  123

6.2 Packaging trends by market 123

6.2.1  Mobile Devices  124

6.2.2  High-Performance Computing (HPC)  125

6.2.3  Automotive 125

6.2.4  Internet of Things (IoT)  125

6.2.5  Consumer Electronics  126

6.2.6  Aerospace and Defense  126

6.2.7  Medical Devices 126

6.3 Design requirements 127

6.4 Artificial Intelligence (AI) 128

6.4.1  Challenges in AI 128

6.4.2  Advanced Packaging Solutions  128

6.4.2.1 2.5D and 3D Integration 128

6.4.2.2 Chiplet-based Packaging 129

6.4.2.3 Wafer-Level Packaging (WLP)  129

6.4.3  Addressing AI Challenges through Advanced Packaging 129

6.4.3.1 Processing Power 129

6.4.3.2 Memory Bandwidth  129

6.4.3.3 Energy Efficiency  129

6.4.3.4 Scalability 130

6.4.4  Applications  130

6.4.4.1 Data Center and Cloud Computing 130

6.4.4.2 Edge Devices and IoT 130

6.4.4.3 Healthcare and Medical Devices 130

6.4.4.4 Autonomous Vehicles 130

6.5 Mobile Devices  131

6.5.1  Challenges 131

6.5.2  Advanced Packaging Solutions  132

6.5.2.1 System-in-Package (SiP) 132

6.5.2.2 Fan-Out Wafer-Level Packaging (FOWLP)  132

6.5.2.3 3D IC Packaging 132

6.5.2.4 Wafer-Level Chip-Scale Packaging (WLCSP)  132

6.5.3  Addressing Challenges through Advanced Packaging 132

6.5.3.1 Power Consumption and Thermal Management  133

6.5.3.2 Size Constraints 133

6.5.3.3 Cost 133

6.5.4  Applications  133

6.5.4.1 Smartphones 133

6.5.4.2 Tablets 133

6.5.4.3 Wearables 134

6.5.4.4 AR/VR Devices 134

6.5.5  Future trends 134

6.6 High Performance Computing (HPC)  135

6.6.1  Challenges 135

6.6.2  Advanced Packaging Solutions for HPC 136

6.6.2.1 2.5D and 3D Integration 136

6.6.2.2 Hybrid bonding  136

6.6.2.3 Multi-Chip Modules (MCMs) 137

6.6.2.4 Chiplet-based Architectures 137

6.6.2.5 Advanced Interconnect Technologies 138

6.6.3  Addressing HPC Challenges through Advanced Packaging  138

6.6.3.1 Performance Scaling 138

6.6.3.2 Power Consumption 138

6.6.3.3 Interconnect Bandwidth 139

6.6.3.4 Reliability  139

6.6.4  Applications  139

6.6.4.1 Supercomputers 140

6.6.4.2 Data Center and Cloud Computing 140

6.6.4.3 Artificial Intelligence and Machine Learning  140

6.6.4.4 Scientific Computing and Simulation  140

6.6.4.5 Co-Packaged Optics 140

6.6.4.5.1 Network Switch  140

6.6.4.5.2 Optical communication in data centers 141

6.6.4.5.3 Thermal Management  141

6.6.4.5.4 Challenges in CPO 141

6.6.4.5.5 Package Structure 141

6.6.4.5.6 Fan-Out Embedded Bridge (FOEB) structure  142

6.6.4.5.7 Advancing Switching and AI Networks 142

6.6.5  Future Trends 143

6.7 Automotive Electronics 144

6.7.1  Challenges 144

6.7.2  Advanced Packaging Solutions for Automotive Electronics  145

6.7.2.1 System-in-Package (SiP) 145

6.7.2.2 Flip-Chip and Wafer-Level Packaging (WLP)  145

6.7.2.3 3D Integration and Through-Silicon Vias (TSVs) 145

6.7.3  Addressing Automotive Electronics Challenges through Advanced Packaging 146

6.7.3.1 ADAS/Autonomous driving systems 146

6.7.3.2 Harsh Environment Reliability  146

6.7.3.3 Safety and Reliability 146

6.7.3.4 Miniaturization and Integration 147

6.7.3.5 High-Speed Communication 147

6.7.3.6 Thermal Management  147

6.7.4  Applications  147

6.7.4.1 Advanced Driver Assistance Systems (ADAS) and Autonomous Driving 147

6.7.4.1.1 Radar packaging  148

6.7.4.2 Electric Vehicle (EV) Power Electronics 149

6.7.4.3 Infotainment and Telematics 149

6.7.4.4 Sensors and Actuators  149

6.7.5  Future Trends 150

6.8 Internet of Things (IoT) Devices 151

6.8.1  Challenges 151

6.8.2  Advanced Packaging Solutions for IoT Devices 152

6.8.2.1 Wafer-Level Packaging (WLP)  152

6.8.2.2 System-in-Package (SiP) 152

6.8.2.3 Fan-Out Wafer-Level Packaging (FOWLP)  152

6.8.2.4 3D Packaging and Through-Silicon Vias (TSVs) 152

6.8.3  Addressing IoT Device Challenges through Advanced Packaging 153

6.8.3.1 Size Constraints 153

6.8.3.2 Power Consumption 153

6.8.3.3 Cost Pressures  153

6.8.3.4 Integration and Functionality 153

6.8.3.5 Reliability and Robustness  153

6.8.4  Applications  154

6.8.4.1 Wearable Devices 154

6.8.4.2 Smart Home Devices 154

6.8.4.3 Industrial IoT Devices 154

6.8.4.4 Medical IoT Devices  154

6.8.5  Future Trends 155

6.9 5G & 6G Communications Infrastructure  156

6.9.1  Challenges 156

6.9.2  Trends in 5G and 6G packaging  156

6.9.3  Advanced Packaging Solutions for 5G and 6G Communications Infrastructure 157

6.9.3.1 Antenna-in-Package (AiP) 157

6.9.3.2 System-in-Package (SiP) 158

6.9.3.3 3D Packaging and Through-Silicon Vias (TSVs) 158

6.9.3.4 Fan-Out Wafer-Level Packaging (FOWLP)  158

6.9.4  Addressing 5G and 6G Infrastructure Challenges through Advanced Packaging 159

6.9.4.1 High-Frequency Operation  159

6.9.4.2 Massive MIMO and Beamforming  160

6.9.4.3 Energy Efficiency  160

6.9.4.4 Cost and Scalability 160

6.9.4.5 Thermal Management  161

6.9.5  Applications  161

6.9.5.1 Base Stations and Small Cells  161

6.9.5.2 Backhaul and Fronthaul Networks 161

6.9.5.3 Edge Computing and Network Slicing 161

6.9.5.4 Satellite and Non-Terrestrial Networks 161

6.9.6  Future Trends 162

6.10 Aerospace and Defense Electronics 163

6.10.1 Challenges 163

6.10.2 Advanced Packaging Solutions for Aerospace and Defense Electronics 164

6.10.2.1  3D Packaging and Through-Silicon Vias (TSVs) 164

6.10.2.2  Chip-Scale Packaging (CSP) and Wafer-Level Packaging (WLP) 164

6.10.2.3  Flip-Chip and Ball Grid Array (BGA) Packaging 164

6.10.2.4  Hermetic Packaging and Sealing 164

6.10.3 Addressing Aerospace and Defense Electronics Challenges through Advanced Packaging 164

6.10.3.1  Size, Weight, and Power (SWaP) Optimization  164

6.10.3.2  Harsh Environment Reliability  165

6.10.3.3  High Performance and Speed  165

6.10.3.4  Long-Term Reliability and Maintainability  165

6.10.3.5  Security and Anti-Tamper Features 165

6.10.4 Applications  166

6.10.4.1  Avionics and Flight Control Systems 166

6.10.4.2  Radar and Electronic Warfare Systems 166

6.10.4.3  Satellite Communications and Payload Electronics  166

6.10.4.4  Missile Guidance and Control Electronics 166

6.10.5 Future Trends 166

6.11 Medical Electronics  168

6.11.1 Challenges 168

6.11.2 Advanced Packaging Solutions for Medical Electronics  168

6.11.2.1  3D Packaging and Through-Silicon Vias (TSVs) 169

6.11.2.2  Wafer-Level Packaging (WLP) and Chip-Scale Packaging (CSP) 169

6.11.2.3  Flexible and Stretchable Packaging 169

6.11.2.4  Microfluidic Packaging  169

6.11.3 Addressing Medical Electronics Challenges through Advanced Packaging  169

6.11.3.1  Miniaturization 169

6.11.3.2  Biocompatibility 170

6.11.3.3  Reliability  170

6.11.3.4  Power Efficiency 170

6.11.3.5  High Performance 170

6.11.4 Applications  171

6.11.4.1  Implantable Devices 171

6.11.4.2  Wearable Health Monitors  171

6.11.4.3  Diagnostic Imaging Equipment 171

6.11.4.4  Surgical Robotics and Instruments 171

6.11.5 Future Trends 172

6.12 Consumer Electronics  173

6.12.1 Challenges 173

6.12.2 Advanced Packaging Solutions for Consumer Electronics 173

6.12.2.1  System-in-Package (SiP) 173

6.12.2.2  Fan-Out Wafer-Level Packaging (FOWLP)  174

6.12.2.3  3D Packaging and Through-Silicon Vias (TSVs) 174

6.12.2.4  Embedded Die Packaging 174

6.12.3 Addressing Consumer Electronics Challenges through Advanced Packaging  174

6.12.3.1  Miniaturization 174

6.12.3.2  Power Efficiency 175

6.12.3.3  High Performance 175

6.12.3.4  Cost Reduction  175

6.12.3.5  Time-to-Market  175

6.12.4 Applications  175

6.12.4.1  Smartphones and Tablets 175

6.12.4.2  Wearables and IoT Devices  176

6.12.4.3  Gaming Consoles and VR/AR Devices 176

6.12.4.4  Smart Home Devices 176

6.12.5 Future Trends 176

6.13 Additive manufacturing for advanced packaging 177

6.14 Silicon photonics 179

 

 

7  GLOBAL MARKET FORECASTS  181

7.1 By type 181

7.2 By Units & Wafers 184

7.3 By market  184

7.4 By region 188

7.5 3D SoC 191

7.6 3D Stacked memory 191

7.7 UHD FO / RDL Interposer 192

7.8 2.5D Interposers 193

7.9 Embedded Si bridge 193

 

 

8.1 Data center 194

8.2 AI and Graphics  195

8.3 CPU 196

8.4 Autonomous vehicles 198

8.5 Roadmap  199

8.5.1  Interconnect technology trend 199

8.5.2  By interconnect density and technology node  199

8.5.3  By reticle size 200

8.5.4  By front-end vs back-end 200

8.5.5  By 2.5D and 3D Technology Trends 201

8.5.6  By I/O density, I/O pitch and package size 202

8.6 Commercialized Products  203

8.6.1  3D Memory 203

8.6.2  GPU 204

8.6.2.1 Nvidia Hopper and Blackwell 204

8.6.2.2 AMD Instinct MI300 series  205

8.6.2.3 Intel Jaguar Shores 206

8.6.3  AI ASICs  206

8.6.3.1 Intel Gaudi 2 & 3 206

8.6.3.2 Google TPU 207

8.6.3.3 Amazon Trainium & Inferentia  208

8.6.3.4 Microsoft Azure Maia 100 209

8.6.3.5 Huawei Ascend Series  209

8.6.4  CPU 210

8.6.4.1 AMD Ryzen AI Max Pro 300  210

8.6.4.2 AMD Ryzen & EPYC  211

8.6.4.3 AWS Graviton 212

8.6.4.4 Intel Emerald Rapids 213

8.6.4.5 Intel Meteor Lake  214

8.6.4.6 Intel Arrow Lake & Lunar Lake  215

 

 

9.1 Integrated Device Manufacturers 217

9.2 Outsourced Semiconductor Assembly and Test (OSAT) Companies 218

9.3 Foundries  220

9.4 Electronics OEMs 223

9.5 Packaging Equipment and Materials Companies 225

 

 

 

Table 1   Evolution of semiconductor packaging     21

Table 2   Summary of key advanced semiconductor packaging approaches  25

Table 3   Key Technology Trends in Advanced Semiconductor Packaging   27

Table 4   Market Growth Drivers for advanced semiconductor packaging  28

Table 5   Challenges Facing Advanced Packaging Adoption       29

Table 6   Challenges in transistor scaling      38

Table 7   Use cases and benefits of using chiplets in semiconductor design  42

Table 8    Specifications of interconnection methods     45

Table 9   Interconnection technique in semiconductor packaging  45

Table 10   Passive vs active interposer      47

Table 11   TSMC Interposer comparison  47

Table 12   Comparative benchmark overview table of key semiconductor interconnection technologies    49

Table 13   Fan-out packaging process overview  53

Table 14   Comparison between mainstream silicon dioxide (SiO2) and leading organic dielectrics for electronic interconnect substrates     56

Table 15   Benefits of glass in 2  5D glass-based packaging  58

Table 16   Comparison between key properties of glass and polymer molding compounds commonly used in semiconductor packaging applications     62

Table 17   Challenges of glass semiconductor packaging     64

Table 18   Comparison between silicon, organic laminates and glass as packaging substrates  64

Table 19   2  5D vs   3D packaging  65

Table 20   2  5D packaging challenges       66

Table 21   Market players in 2  5D packaging   67

Table 22   Advantages and disadvantages of 3D packaging       69

Table 23   Comparison between 2  5D, 3D micro bump, and 3D hybrid bonding     72

Table 24   Challenges in 3D Hybrid Bonding   72

Table 25   Challenges in scaling bumps   74

Table 26   Key methods for enabling copper-to-copper (Cu-Cu) hybrid bonding in advanced semiconductor packaging:  75

Table 27   Micro bumps vs Cu-Cu bumpless hybrid bonding     75

Table 28   W2W vs D2W vs collective D2W ? process and comparison    78

Table 29   Comparison of WLP and PLP for large package size 79

Table 30   Benefits of Wafer-Level Packaging       79

Table 31   Types of wafer level packaging     80

Table 32   Key trends shaping wafer level packaging       95

Table 33   Packaging approaches utilized for assembling System-in-Package modules    101

Table 34   Considerations for integrating key component categories into system-in-package (SiP) modules/    104

Table 35   Key factors driving adoption of heterogeneous integration through SiPs and multi-die packages    105

Table 36   Key trends influencing adoption of System-in-Package modules    105

Table 37    System-in-package (SiP) module applications     107

Table 38   Comparison between heterogeneous 3D integration and monolithic 3D integration    116

Table 39    Key 2D materials in monolithic 3D integrated circuits   116

Table 40   Benefits of monolithic 3D ICs  118

Table 41   Challenges of monolithic 3D ICs     118

Table 42   Advanced semiconductor packaging trends by market    123

Table 43   Design requirements in advanced packaging, by market      127

Table 44   Global market for Advanced semiconductor packaging, 2020-2035, by packaging type, (billions USD)     181

Table 45   Global market for Advanced semiconductor packaging, 2020-2035, by Units & Wafers, (billions USD)     184

Table 46   Global market for Advanced semiconductor packaging, 2020-2035, by end use market (billions USD)     185

Table 47   Recent expansion activities by companies in Malaysia    188

Table 48   Global market for Advanced semiconductor packaging, 2020-2035, by region (billions USD)      189

Table 49   Main Global Wafer Foundry Companies 2023    221

Table 50   Market challenges for advanced semiconductor packaging     226

Table 51   AMD AI chip range     231

Table 52    Intel's products that adopt 3D FOVEROS  274

 

 

Figure 1   Timeline of different packaging technologies 22

Figure 2   Evolution roadmap for semiconductor packaging      24

Figure 3   Semiconductor Supply Chain  26

Figure 4   Advanced packaging supply chain  27

Figure 5   Scaling technology roadmap    38

Figure 6   Wafer-level chip scale packaging (WLCSP)     39

Figure 7   Embedded wafer-level ball grid array (eWLB) 40

Figure 8   Fan-out wafer-level packaging (FOWLP)     41

Figure 9   Chiplet design     42

Figure 10   Chiplet SoC       44

Figure 11   2D chip packaging  50

Figure 12   Typical structure of 2  5D IC package utilizing interposer      51

Figure 13   Fan-out chip-first process flow and Fan-out chip-last process flow   55

Figure 14   Manufacturing process for glass interposers     60

Figure 15   3D Glass Panel Embedding (GPE) package  62

Figure 16   Typical FOWLP structure     83

Figure 17   System-in-Package (SiP) for HI    99

Figure 18   2  5D chiplet integration   102

Figure 19   Advanced packaging supply chain     121

Figure 20   Packaging of sensors used in advanced driver assistance systems (ADAS) and autonomous driving     150

Figure 21   Global market for Advanced semiconductor packaging, 2020-2035, by packaging type, (billions USD)     183

Figure 22   Global market for Advanced semiconductor packaging, 2020-2035, by Units & Wafers, (billions USD)     184

Figure 23   Global market for Advanced semiconductor packaging, 2020-2035, by end use market (billions USD)     187

Figure 24   Global market for Advanced semiconductor packaging, 2020-2035, by region (billions USD)      190

Figure 25   Absolic glass substrate    229

Figure 26   AMD Radeon Instinct   231

Figure 27   AMD Ryzen 7040   231

Figure 28   Alveo V70   231

Figure 29   Versal Adaptive SOC    232

Figure 30   AMD’s MI300 chip    232

Figure 31   12-layer HBM3 305