目次
価格・ご注文について 価格についてはデータリソースまでお問い合わせください
この調査レポートは、フラッシュメモリと代替不揮発メモリのコスト動向を調査しています。下記などの様々なメモリ技術について、2013年までのコストと平均販売価格を予測しています。
- DRAM
- SRAM
- シングル/マルチレベルセルNORフラッシュ
- ミラービット
- NROM
- クアッドNROM
| - シングルレベル/マルチレベルセル 3ビット/4ビット/セルNANDフラッシュ
- FRAM
- MRAM
- 相変化メモリ
|
また、下記のウエハーコストの見込み額とダイサイズについても調査しています
- ナノクリスタルメモリ
- STT-RAM
- PFRAM
- ナノチューブメモリ
- RRAM
- プローブメモリ
下記のような様々なメモリ別に、設計と製造を分析しています。
- DRAM
- SRAM/PSRAM
- シングルレベルセル NOR型
- マルチレベルセル NOR型
- ナノクリスタル
- シングルレベルセル NAND型
- マルチレベルセル NAND型
- 3ビット/セルのNAND型
- 2ビット/セルのNAND型
- NAND型クアッドメモリ
- MirrorBit
| - NROM
- NROMクアッド
- FRAM (1T1C)
- MRAM
- CRAM
- PFRAM
- nanoRAM
- RRAM
- プローブメモリ
|
TOP
Table of Contents
Structure
Table of Contents
List of Figures
List of Tables
List of Appendices
1 Key Observations and Conclusions
2 Methodology, Formulae, Technical Notes
3 Definition of Terms, Glossary
3.1 Market Manufacturing Parameters
3.2 Chip and Package - Physical/Electrical Parameters
3.3 Electric and Test Parameters
4 Objectives and Scope, Analysis Approach, Underlying Assumptions, Reporting Format
4.1 Objectives and Scope
4.2 Analysis Approach
4.2.1 Die Cost / Component Cost / Gross Margins Calculation Methodology
4.3 Underlying Assumptions
4.3.1 Definition of New Product/Technology Introduction Year
4.3.2 Assumptions for the Design and Manufacturing Technology Area
4.3.3 Gross Margin and Market Price Assumptions
4.4 Reporting Format
5 A Manufacturing Perspective on Nonvolatile Memory Technologies
5.1 Design and Front-End Manufacturing Technology Considerations
5.1.1 Some Fundamental Front-End Process Limits and Long-Term Solutions
5.1.2 Evolutionary Front-End Manufacturing Developments
5.2 Back-End Manufacturing Technology Considerations
5.2.1 Testing
5.2.2 Assembly and Packaging
6 Analysis Methodology and Assumptions
6.1 Analysis Methodology
6.2 Analysis Assumptions
6.2.1 Wafer Cost Assumptions
6.2.2 Storage Density Assumptions
6.2.3 Die Size Assumptions
6.2.4 Dies per Wafer and Die Yield Assumptions
6.2.5 Die Cost Assumptions
6.2.6 Component Cost Assumptions
6.2.7 Market Price Assumptions
6.2.8 Gross Margin Assumptions
6.2.9 Die Cost / Component Cost / Gross Margins Calculation Methodology
7 Analysis Results
7.1 DRAM Design and Manufacturing Analysis
7.1.1 Analysis Results
7.1.2 Summarizing Remarks
7.2 SRAM/PSRAM Design and Manufacturing Analysis
7.2.1 Analysis Results
7.2.2 Summarizing Remarks
7.3 SLC NOR Design and Manufacturing Analysis
7.3.1 Analysis Results
7.3.2 Summarizing Remarks
7.4 MLC NOR Design and Manufacturing Analysis
7.4.1 Analysis Results
7.4.2 Summarizing Remarks
7.5 nanoFG Design and Manufacturing Analysis
7.5.1 Analysis Results
7.5.2 Summarizing Remarks
7.6 SLC NAND Design and Manufacturing Analysis
7.6.1 Analysis Results
7.6.2 Summarizing Remarks
7.7 MLC NAND Design and Manufacturing Analysis
7.7.1 Analysis Results
7.7.2 Summarizing Remarks
7.8 3-bit per cell NAND Design and Manufacturing Analysis
7.8.1 Analysis Results
7.8.2 Summarizing Remarks
7.9 NAND Quad Design and Manufacturing Analysis
7.9.1 Analysis Results
7.9.2 Summarizing Remarks
7.10 MirrorBit Design and Manufacturing Analysis
7.10.1 Analysis Results
7.10.2 Summarizing Remarks
7.11 NROM Design and Manufacturing Analysis
7.11.1 Analysis Results
7.11.2 Summarizing Remarks
7.12 NROM Quad Design and Manufacturing Analysis
7.12.1 Analysis Results
7.12.2 Summarizing Remarks
7.13 FRAM (1T1C) Design and Manufacturing Analysis
7.13.1 Analysis Results
7.13.2 Summarizing Remarks
7.14 MRAM Design and Manufacturing Analysis
7.14.1 Analysis Results
7.14.2 Summarizing Remarks
7.15 MRAM Design and Manufacturing Analysis
7.15.1 Analysis Results
7.15.2 Summarizing Remarks
7.16 CRAM Design and Manufacturing Analysis
7.16.1 Analysis Results
7.16.2 Summarizing Remarks
7.17 PFRAM Design and Manufacturing Analysis
7.17.1 Analysis Results
7.17.2 Summarizing Remarks
7.18 nanoRAM Design and Manufacturing Analysis
7.18.1 Analysis Results
7.18.2 Summarizing Remarks
7.19 RRAM Design and Manufacturing Analysis
7.19.1 Analysis Results
7.19.2 Summarizing Remarks
7.20 Probe Memory Design and Manufacturing Analysis
7.20.1 Analysis Results
7.20.2 Summarizing Remarks
8 Appendices
9 About Web-Feet Research
List of Figures
Figure 1 Die cost / component cost / gross margin calculation methodology
Figure 2 Definition of the new product introduction year
Figure 3 Relative chip size / cost dependency
Figure 4 Improvement ratios for number of dies
Figure 5 μBGA package cross section
Figure 6 FBGA package cross section
Figure 7 EasyBGA package cross section
Figure 8 Stacked-CSP package cross section
Figure 9 Flip-chip for chip-on-board/chip-on-glass mounting procedure
Figure 10 Wafer exclusion edges
Figure 11 Relative die cost breakdown
Figure 12 Die cost / component cost / gross margin calculation methodology
Figure 13 DRAM market price forecast - 2007-2013
Figure 14 SRAM/PSRAM market price forecast - 2007-2013
Figure 15 SLC NOR market price forecast - 2007-2013
Figure 17 MLC NOR market price forecast - 2007-2013
Figure 17 SLC NAND market price forecast - 2007-2013
Figure 18 MLC NAND market price forecast - 2007-2013
Figure 19 3-BIT PER CELL NAND market price forecast - 2007-2013
Figure 20 NAND QUAD market price forecast - 2007-2013
Figure 21 MirrorBit market price forecast - 2007-2013
Figure 23 NROM market price forecast - 2007-2013
Figure 23 NROM Quad market price forecast - 2007-2013
Figure 24 FRAM (1T1C) market price forecast - 2007-2013
Figure 25 MRAM market price forecast - 2007-2013
Figure 26 CRAM market price forecast - 2007-2013
Figure 27 nanoRAM market price forecast - 2007-2013
Figure 28 RRAM market price forecast - 2007-2013
List of Tables
Table 1 Scenarios for technology node evolution
Table 2 Reporting format for trends
Table 3 Reporting format for manufacturing data
Table 4 Design and manufacturing technology node forecast (3 year pace)
Table 5 Manufacturing cycle time reduction
Table 6 Design cost evolution
Table 7 Incremental mask layer number for multi-technology integration
Table 8 Wafer size roadmap
Table 9 Interconnect roadmap for mature semiconductor technologies
Table 10 Correlation among chip assembly and packaging costs, pin count and performance
Table 11 SOP family characteristics
Table 12 CSP family member specifications
Table 13 BGA package pin count and solder ball pitch
Table 14 Die pad pitch forecast
Table 15 Relative package cost comparison
Table 16 DRAM wafer cost - 2007-2013
Table 17 DRAM die capacity / die size / cost - 2007-2013
Table 18 SRAM/PSRAM wafer cost - 2007-2013
Table 19 SRAM/PSRAM die capacity / die size / cost - 2007-2013
Table 20 SLC NOR wafer cost - 2007-2013
Table 21 SLC NOR die capacity / die size / cost - 2007-2013
Table 22 MLC NOR wafer cost - 2007-2013
Table 23 MLC NOR die capacity / die size / cost - 2007-2013
Table 24 nanoFG wafer cost - 2007-2013
Table 25 nanoFG die capacity / die size - 2007-2013
Table 26 SLC NAND wafer cost - 2007-2013
Table 27 SLC NAND die capacity / die size / cost - 2007-2013
Table 28 MLC NAND wafer cost - 2007-2013
Table 29 MLC NAND die capacity / die size / cost - 2007-2013
Table 30 3-BIT PER CELL NAND wafer cost - 2007-2013
Table 31 3-BIT PER CELL NAND die capacity / die size / cost - 2007-2013
Table 32 NAND QUAD wafer cost - 2007-2013
Table 33 NAND QUAD die capacity / die size / cost - 2007-2013
Table 34 MirrorBit wafer cost - 2007-2013
Table 35 MirrorBit die capacity / die size / cost - 2007-2013
Table 36 NROM wafer cost - 2007-2013
Table 37 NROM die capacity / die size / cost - 2007-2013
Table 38 NROM Quad wafer cost - 2007-2013
Table 39 NROM Quad die capacity / die size / cost - 2007-2013
Table 40 FRAM (1T1C) wafer cost - 2007-2013
Table 41 FRAM (1T1C) die capacity / die size / cost - 2007-2013
Table 42 MRAM wafer cost - 2007-2013
Table 43 MRAM die capacity / die size / cost - 2007-2013
Table 44 STT-RAM wafer cost - 2007-2013
Table 45 STT-RAM die capacity / die size - 2007-2013
Table 46 CRAM wafer cost - 2007-2013
Table 47 CRAM die capacity / die size / cost - 2007-2013
Table 48 PFRAM wafer cost - 2007-2013
Table 49 PFRAM die capacity / die size - 2007-2013
Table 50 nanoRAM wafer cost - 2007-2013
Table 51 nanoRAM die capacity / die size - 2007-2013
Table 52 RRAM wafer cost - 2007-2013
Table 53 RRAM die capacity / die size - 2007-2013
Table 54 Probe Memory wafer cost - 2007-2013
Table 55 Probe Memory die capacity / die size - 2007-2013
List of Appendices
Appendix 1 Front-end manufacturing flow
Appendix 2 Back-end manufacturing flow
Appendix 3 Front-end manufacturing steps
Appendix 4 Back-end manufacturing steps - side-pin packages
Appendix 5 Back-end manufacturing steps - chip scale packages
