目次
価格・ご注文について 半導体材料専門の米国の調査会社テクセット社の調査レポート「インターコネクト材料市場調査 2009年版 - Interconnect Metallization Materials for 65nm through 22nm Nodes」は、 65nmから22nmノードに使用されているインターコネクト材料市場について、調査・分析し、市場規模や収益の予測などを提供しています。
Table of Contents
1 BACKGROUND AND TECHNOLOGY OVERVIEW
1.1 Interconnect Trends
1.2 Factors Driving the Change from Al to Cu wiring
1.3 Interconnect Processes
1.4 Process Flows for Interconnect by IC Product and Generation
1.5 Roadmap Implications
1.6 Process Flows
2 INTERCONNECT PROCESS MATERIAL DESCRIPTIONS
2.1 Metal Filled Contact Plugs.
2.2 Metal (Copper) for Interconnect Wiring .
2.2.1 Copper Plating Baths .
2.2.2 Copper Plating Equipment Suppliers .
2.2.3 Copper Electroplating Chemistry Suppliers.
2.2.4 Electroplating Bath Supply Chain Status
2.3 Integrated Barrier Seed, PVD
2.4 Copper Cap after CMP
3 INTERCONNECT MATERIALS FORECAST MARKET SIZES
3.1 Metal Filled Contact Plugs.
3.2 Barrier Metal for Copper Wiring.
3.3 Copper Metal for Interconnect Wiring
3.4 Copper Cap and Cap Barrier Dielectric
FIGURES
Figure 1: Percentage of Wafers with Cu Interconnects by Technology Node and Product Type
Figure 2: Circuit Delay as a Function of Feature Size.
Figure 3: RC Delay, Cu, & Low κ .
Figure 4: Al Wire with Oxide Dielectric.
Figure 5: Cu Dual Damascene with Oxide Dielectric
Figure 6: Process Sequence for Cu Dual Damascene.
Figure 7: Process Sequence for ICs from PMD through W Plug Fill of Contacts
Figure 8: Process Sequence for Al-Cu ICs, All Metal Layers Processed Similarly .
Figure 9: Process Sequence for Copper Wiring ICs for First Metal Formation.
Figure 10: Process Sequence for Copper ICs for Each Metal Level Beyond M1.
Figure 11: Process Sequence Options for Copper Wiring (PAR is Poly Arylene)
Figure 12: κeff Roadmap Delay as Explained in the 2007 ITRS
Figure 13: 65 nm Potential Integration Schemes (2007 & 2008 Realistic Case) .
Figure 14: World Wide Electroplating Bath Market Share by Supplier
Figure 15: Revenue Forecast for Only WF6 at 90nm through 22nm
Figure 16: Revenue Forecast for Only TDMAT at 90nm through 22nm nodes
Figure 17: Ta Barrier Sputter Target Revenues
Figure 18: ALD Metal Barrier Forecast
Figure 19: Copper Plating Bath Projections by Technology Node and Product Type
Figure 20: Revenue Opportunity for CoWP or CoWB
TABLES
Table 1: Materials & Process Options for 2013 (32 nm) & 2016 (22 nm)
Table 2: Properties of Metals
Table 3: 2008 update of 2007 ITRS for MPU Interconnect Technology Requirements
Table 4: 2008 update of 2007 ITRS DRAM Interconnect Technology Requirements
